公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2000183302A

公开(公告)日：2000-06-30

申请号：JP35805299

申请日：1999-12-16

Applicant: IBM ,  SIEMENS AG

Inventor： SUSAN E SHARUU ,  TSUE CHIAN CHEN ,  JONATHAN E FALTERMAIER ,  GRUENING ULRIKE ,  RAJARAAO JANMII ,  MANDELMAN JACK A ,  PARKS CHRISTOPHER C ,  PAUL C PARIIZU ,  PAUL A RONSUHAIMU ,  YUN YUU WAN

IPC: B82B1/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a trench capacitor structure in which mutual influence can be reduced between the regions whose crystallization levels are different. SOLUTION: In a trench capacitor 40, a substrate 60 is provided with a trench 44, an embedded plate electrode 42, a node dielectric 46, an oxide collars 48, trench electrode materials 50, and a conductive type strap 56. A quantum conductive layer which is a silicon nitride thin film is arranged on a boundary face 58 between the conductive strap 56 and the substrate 60 and a boundary face 62 between the trench electrode 50 and the conductive strap 56. The transmission of the recrystallizing force of the trench electrode 50 and the strap 56 to the strap 56 or the substrate 60 can be reduced by this quantum conductive layer. Thus, the reliability of the device can be improved.

公开(公告)号：JP2000091525A

公开(公告)日：2000-03-31

申请号：JP25944099

申请日：1999-09-13

Applicant: IBM

Inventor： JAMMY RAJARAO ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory structure, especially a deep trench semiconductor memory device for which a temperature sensitive high dielectric constant material is taken inside the storage node of a capacitor. SOLUTION: In this manufacturing method, after shallow trench separation at high temperature and processing a gate conductor, a deep trench storage capacitor is manufactured. With the manufacturing method, a temperature sensitive high dielectric constant material can be taken into a capacitor structure without causing decomposition of the material. Furthermore, the manufacturing method limits the spread of a buried strap outward diffused part 44, and thus the electric characteristics of an array MOSFET are improved.

公开(公告)号：JPH10256394A

公开(公告)日：1998-09-25

申请号：JP3865098

申请日：1998-02-20

Applicant: IBM

Inventor： DONALD C WHEELER ,  LEWIS L SUU ,  MANDELMAN JACK A ,  REBECCA D MI

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a new structure, especially a CMOS structure, decreasing off-state current of a device. SOLUTION: A MOS transistor 70 contains two trench isolation regions 78 adjoining an active region 79. The trench isolation regions 78 is disposed on the opposite sides of the active region 79 so that side walls 80 of each trench acts as an interface for the active region 79, and at least one of the side walls 80 has inclination of 90-150 deg.. The trench isolation regions 78, a source injection region and a drain injection region 78 surround all sides of the active region 79.

公开(公告)号：JPH1074907A

公开(公告)日：1998-03-17

申请号：JP16576497

申请日：1997-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased.

公开(公告)号：MY121158A

公开(公告)日：2005-12-30

申请号：MYPI20003023

申请日：2000-07-03

Applicant: IBM

Inventor： HARGROVE MICHAEL J ,  MANDELMAN JACK A

IPC: H01L21/28 ,  H01L27/01 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: A STRUCTURE AND PROCESS FOR MAKING A SEMICONDUCTOR DEVICE WITH SOI BODY CONTACTS UNDER THE GATE CONDUCTOR.THE GATE CONDUCTER IS PARTITIONED INTO SEGMENTS AND PROVIDES A BODY CONTACT UNDER EACH GATE CONDUCTER SEGMENT OVER THE WIDTH OF THE DEVICE. A PLURALITY OF BODY CONTACTS MAY BE DISTRIBUTED ACROSS THE LENGTH OF THE GATE CONDUCTER.THIS RESULTS IN A RELATIVELY SHORT PATH FOR HOLES LEAVING THE BODY TO TRAVERSE AND ALLOWS ACCUMULATED CHARGE TO BE REMOVED FROM THE BODY REGION UNDER THE GATE.THE STRUCTURE PROVIDES FOR STABLE AND EFFICIENT BODY-CONTACT OPERATION FOR SOI MOSFETS OF ANY WIDTH OPERATING AT HIGH SPEEDS.FIG. 13

公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

公开(公告)号：HK1032293A1

公开(公告)日：2001-07-13

申请号：HK01102845

申请日：2001-04-23

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： RAMA DIVAKARUNI ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L

Abstract: The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.

公开(公告)号：DE10350703B4

公开(公告)日：2009-04-02

申请号：DE10350703

申请日：2003-10-30

Applicant: IBM ,  QIMONDA AG

Inventor： MANDELMAN JACK A ,  CHUDZIK MICHAEL ,  SEITZ MIHEL

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/329 ,  H01L29/94

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.