中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

111 records (took 0.023 seconds)

    61.
    发明专利
    未知

    公开(公告)号：DE19524478C2

    公开(公告)日：2002-03-14

    申请号：DE19524478

    申请日：1995-07-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOFMANN FRANZ ,  ROESNER WOLFGANG ,  KRAUTSCHNEIDER WOLFGANG ,  RISCH LOTHAR

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

    Abstract: PCT No. PCT/DE96/01117 Sec. 371 Date Dec. 8, 1997 Sec. 102(e) Date Dec. 8, 1997 PCT Filed Jun. 25, 1996 PCT Pub. No. WO97/02599 PCT Pub. Date Jan. 23, 1997An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.

    65.
    发明专利
    未知

    公开(公告)号：DE59814314D1

    公开(公告)日：2008-12-11

    申请号：DE59814314

    申请日：1998-07-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS ,  ROESNER WOLFGANG ,  RISCH LOTHAR

    IPC: H01L29/78 ,  H01L21/336

    Abstract: A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

    66.
    发明专利
    未知

    公开(公告)号：DE59914630D1

    公开(公告)日：2008-03-13

    申请号：DE59914630

    申请日：1999-12-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  RAMCKE TIES ,  RISCH LOTHAR

    IPC: H01L21/768 ,  H01L27/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/00 ,  H01L27/092 ,  H01L27/10 ,  H01L29/06 ,  H01L29/76

    Abstract: At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.

    68.
    发明专利
    未知

    公开(公告)号：DE102004033147B4

    公开(公告)日：2007-05-03

    申请号：DE102004033147

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.

Patent Agency Ranking