公开(公告)号：DE19842852B4

公开(公告)日：2005-05-19

申请号：DE19842852

申请日：1998-09-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C7/08 ,  G11C8/08 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4091 ,  H01L27/105 ,  H01L27/108 ,  G11C11/407

公开(公告)号：DE10339894A1

公开(公告)日：2005-03-31

申请号：DE10339894

申请日：2003-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C11/4091

Abstract: The apparatus includes a switch unit for connecting a reader amplifier unit to a bit line or a cell field region and for disconnecting the amplifier from the bit line or cell field region in dependence on the state of a control signal on a control line. The apparatus also has a driver to drive the control signal. An additional switch is provided which can cause a change in state of the control signal applied to the control line. Independent claims also cover a method of operating the apparatus.

公开(公告)号：DE50009385D1

公开(公告)日：2005-03-10

申请号：DE50009385

申请日：2000-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SCHNEIDER HELMUT

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108

Abstract: A decoder connection configuration for memory chips, in which, in a dummy region of a decoder, the dummy region being caused by a bit line twist, additional plated-through holes are provided between power supply lines and the decoder. By virtue of the bit line twist, the coupling capacitance is practically halved on account of the electrical symmetry.

公开(公告)号：DE10320795A1

公开(公告)日：2004-12-09

申请号：DE10320795

申请日：2003-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  BREDE RUEDIGER

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/017

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

公开(公告)号：DE10203152C1

公开(公告)日：2003-10-23

申请号：DE10203152

申请日：2002-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  ACHARYA PRAMOD ,  KIESER SABINE ,  GRAESSER URSULA ,  SCHNEIDER HELMUT ,  MARKERT MICHAEL

IPC: G11C8/08 ,  H01L27/108 ,  H01L27/105

Abstract: The memory device (100) has at least one memory module and associated word decoder block and at least one driver transistor pair (101a,101b), coupled to the word decoder block at their gates (104) in a ring structure (RDC). The sources (102) of the driver transistor pair lie outside the ring structure and have a common diffusion zone, the drains lying within the ring structure and coupled to at least one memory row selection line (106a,106b), adjacent selection lines coupled via a coupling transistor (105) receiving the same gate signal as the driver transistor pair.

公开(公告)号：DE10204688C1

公开(公告)日：2003-10-09

申请号：DE10204688

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  OHLHOFF CARSTEN ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L31/119

Abstract: A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

公开(公告)号：DE10107141A1

公开(公告)日：2002-08-29

申请号：DE10107141

申请日：2001-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRIMM WOLFGANG ,  SCHNEIDER HELMUT

IPC: H04L25/08 ,  H03K5/00 ,  H04B3/32

Abstract: The method involves using a coupling capacitance formed between two conducting tracks (A,B) and a first signal (PHI A) formed on the first of the two conducting tracks, whereby the electrical circuit element (1) is arranged on the second conducting track. The time variation of a second signal is accelerated by the control exerted on the circuit element. Independent claims are also included for the following: an electrical circuit with two conducting tracks and at least one circuit element.

公开(公告)号：DE10102000A1

公开(公告)日：2002-08-01

申请号：DE10102000

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  SCHNEIDER HELMUT

IPC: H01L23/50 ,  H01L23/544 ,  H01L23/58

Abstract: A description is given of an integrated circuit having components and a method for checking a connection configuration of bonding pads. The integrated circuit has an identification circuit that identifies a connection of the bonding pads to external circuits. After the identification of the connected bonding pads, the data width of the input/output circuit is preferably programmed accordingly. In this way, self-detection and automatic programming are possible without data inputting from the outside.

公开(公告)号：DE10006236C2

公开(公告)日：2001-12-20

申请号：DE10006236

申请日：2000-02-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT ,  KRASSER HANS-JUERGEN

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  H03K5/13 ,  H03K5/131 ,  H03K5/133 ,  G01R31/3187 ,  H03K5/14

Abstract: In the configuration, the module can "learn" one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals, for instance, for the purpose of evaluating whether the module in question has crossed a time specification value or remains below the value. The module can also measure and store one or more internal time intervals and transmit them to the external tester in digital or analog form.

公开(公告)号：DE10026251A1

公开(公告)日：2001-12-06

申请号：DE10026251

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  H01L23/525 ,  H01L27/105 ,  G11C17/14

Abstract: The fuse or anti-fuse programming device uses application of an electrical voltage (V1-V2) for destruction of the fuse or anti-fuse (1), with the latter connected in series between the source-drain paths of at least 2 transistors (T1,T2), e.g. a p-channel FET and a n-channel FET positioned on opposite sides of the fuse.