公开(公告)号：DE69727937D1

公开(公告)日：2004-04-08

申请号：DE69727937

申请日：1997-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

IPC: G11C11/41 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

公开(公告)号：DE69911591D1

公开(公告)日：2003-10-30

申请号：DE69911591

申请日：1999-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  CRIPPA LUCA

IPC: G11C16/06 ,  G11C16/28 ,  G11C7/06

公开(公告)号：DE69627142T2

公开(公告)日：2003-10-16

申请号：DE69627142

申请日：1996-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： GHILARDELLI ANDREA ,  CAMPARDO GIOVANNI ,  MULATTI JACOPO

IPC: G11C5/14 ,  G11C16/06

Abstract: A charge pump comprises at least one charge pump stage (S1-Sn) comprising a first diode (D1-Dn) having an anode (A) and a cathode (K), and a capacitor (C1-Cn) having a first plate connected to the cathode (K) of the diode (D1-Dn) and a second plate connected to a clock signal (CK1,CK2) periodically varying between a reference voltage and a supply voltage (VDD), the anode (A) of said diode (D1-Dn) forming a first terminal (NEG) of the charge pump. The charge pump comprises a second diode (Dn+1) having an anode (A) connected to the cathode (K) of the first diode (D1-Dn) and a cathode (K) forming a second terminal (POS) of the charge pump, first switching means (SW1) for selectively coupling the first terminal (NEG) of the charge pump to the voltage supply (VDD) and second switching means (SW2) for selectively coupling the second terminal (POS) of the charge pump to the reference voltage. The first switching means (SW1) and the second switching means (SW2) are respectively closed and open in a first operating condition whereby the second terminal (POS) of the charge pump acquires a voltage of the same sign but higher in absolute value than said supply voltage (VDD). The first switching means (SW1) and the second switching means (SW2) are respectively open and close in a second operating condition whereby the first terminal (NEG) of the charge pump acquires a voltage of opposite sign with respect to said voltage supply (VDD).

公开(公告)号：DE69629668D1

公开(公告)日：2003-10-02

申请号：DE69629668

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO

IPC: G11C16/06 ,  G11C16/28

公开(公告)号：DE69909969D1

公开(公告)日：2003-09-04

申请号：DE69909969

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MANSTRETTA ALESSANDRO ,  MICHELONI RINO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: Non-volatile memory device organised with memory cells that are arranged by row and by column, comprising at least a sector of matrix cells (100), row decoders (D) and column decoders suitable to decode address signals and to activate respectively said rows or said columns, at least a sector of redundancy cells (110) such that it is possible to substitute a row of said sector of matrix cells with a row of said sector of redundancy cells. Said non-volatile memory device comprises a local column decoder (L) for said matrix sector (100) and a local column decoder (L) for said redundancy sector (110). The local column decoders (L) are controlled by external signals so that said row of said redundancy sector (110) is activated simultaneously with said row of said matrix sector (100).

公开(公告)号：DE69624230T2

公开(公告)日：2003-02-13

申请号：DE69624230

申请日：1996-07-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  GOLLA CARLA

IPC: H03K19/003 ,  H03K17/00

Abstract: An output stage (1) for electronic circuits (2) with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair (Pu,Nu) comprising a P-channel MOS pull-up transistor (Pu) and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal (U) of the stage which comprises in addition a switch (6) having an input (8) connected to the output terminal (U) of the stage and an output (9) connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

公开(公告)号：DE69526789T2

公开(公告)日：2002-11-21

申请号：DE69526789

申请日：1995-09-29

Applicant: ST MICROELECTRONICS SRL

Inventor： BRANCHETTI MAURIZIO ,  GOLLA CARLA ,  CAMPARDO GIOVANNI

IPC: G06F11/10

公开(公告)号：DE69426487T2

公开(公告)日：2001-06-07

申请号：DE69426487

申请日：1994-03-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34

Abstract: To reduce the supply voltage (VCC) of a nonvolatile memory (48), a read reference signal (H) is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic (H) of the read reference signal is composed of two portions: a first portion (H1), ranging between the threshold value and a predetermined value (Vs), presents a slope lower than that of the characteristic (A, G) of the memory cells (50); and a second portion (H2), as of the predetermined value of the supply voltage, presents the same slope as the memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells (11-13) so biased as to see bias voltages lower than the supply voltage.

公开(公告)号：DE69520665D1

公开(公告)日：2001-05-17

申请号：DE69520665

申请日：1995-05-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  BEDARIDA LORENZO ,  FUSILLO GIUSEPPE ,  SILVAGNI ANDREA

IPC: G11C17/00 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00 ,  G11C7/00

公开(公告)号：DE69325442D1

公开(公告)日：1999-07-29

申请号：DE69325442

申请日：1993-03-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: To reduce the number of depleted cells (21) and the errors caused thereby, the memory array (20) comprises a number of groups of control transistors (23) relative to respective groups (22) of memory cells. The control transistors (23) of each group are NMOS transistors having the drain terminal connected to its own control line (BLP), and each of the control transistors of one group is relative to a row portion of the memory array (20): More specifically, each control transistor (23) presents the control gate connected to the respective word line (WL), and the source region connected to the source region of the cells (21) in the same row and in the same group (22).