公开(公告)号：WO99031777A1

公开(公告)日：1999-06-24

申请号：PCT/JP1998/005488

申请日：1998-12-04

IPC: H02G3/08 ,  H02G3/16 ,  H02G5/00 ,  H05K3/20 ,  H05K3/32 ,  H05K7/06

CPC classification number: H02G3/16 ,  H02G3/081 ,  H02G5/005 ,  H05K3/202 ,  H05K3/326 ,  H05K2201/091 ,  H05K2201/10946 ,  H05K2201/2072 ,  Y10S439/949 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49833 ,  Y10T29/49845 ,  Y10T29/49908

Abstract: A bus bar wiring board comprising a bus bar pattern for electric wiring formed in a predetermined shape, and a bus bar piece formed separately from the bus bar pattern and electrically connected and secured to the bus bar pattern. A method of producing the bus bar wiring board comprising a bus bar pattern punching step for punching a bus bar pattern for electric wiring that is laid out in a predetermined shape out of an electrically conducting metal plate, a bus bar piece punching step for punching a bus bar piece laid out in a predetermined shape in a remaining space on the electrically conducting metal plate, and a connection step for electrically connecting and securing together the bus bar pattern punched in the bus bar pattern punching step and the bus bar pieve punched in the bus bar piece punching step, whereby reducing the waste in the electrically conducting metal plate out of which the bus bar patterns are punched and decreasing the cost of production or the cost of a product.

Abstract translation: 一种汇流条布线板，包括形成为预定形状的电线的母线图形，以及与母线图案分开形成的母线条，并且电连接并固定到母线图案。 一种母线布线板的制造方法，其特征在于，包括：母线条冲孔工序，用于冲压导电金属板中以规定形状布置的电气布线的母线图形;冲压步骤 在导电金属板上的剩余空间中以预定形状布置的母线条，以及连接步骤，用于将冲压在母线图案冲压步骤中的母线图形和将冲压在母线条冲压步骤中的母线棒电连接并固定在一起 母线冲压步骤，从而减少导电金属板中的浪费，其中冲压母线图案并降低生产成本或产品成本。

公开(公告)号：WO98050954A1

公开(公告)日：1998-11-12

申请号：PCT/US1998/009442

申请日：1998-05-08

IPC: B23K20/00 ,  C25D7/12 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/603 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H05K1/14 ,  H05K3/20 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40

CPC classification number: B23K20/004 ,  B23K2101/40 ,  C25D7/12 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/141 ,  H05K3/20 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00014

Abstract: High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices (402, 404, 406, 408) atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements (422, 424, 426, 428) extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate (430), such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes (432, 434, 436, 438). The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., a nickel plating).

Abstract translation: 通过将半导体器件（402,404,406,408）彼此顶起堆叠来实现半导体器件在互连衬底上的高密度封装，使得半导体器件的边缘部分延伸超过其顶部堆叠的半导体器件。 细长的互连元件（422,424,426,428）从半导体器件的最底端延伸，并且从半导体器件的暴露的边缘部分堆叠在最底层的半导体器件的顶部。 细长互连元件的自由端与诸如PCB的互连衬底（430）的端子电接触。 从每个半导体器件延伸的细长互连元件的尺寸被设计成到达可以通过孔（432,434,436,438）电镀的PCB的端子。 细长互连元件是合适的弹性接触结构，并且可以是包括相对软的芯（例如，金线）和相对硬的外涂层（例如镀镍）的复合互连元件。

公开(公告)号：WO1997037373A2

公开(公告)日：1997-10-09

申请号：PCT/US1997004911

申请日：1997-03-27

Applicant: CERIDIAN CORPORATION

Inventor： CERIDIAN CORPORATION ,  PAI, Deepak, Keshav

IPC: H01L00/00

CPC classification number: H05K3/303 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/3426 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10946 ,  H05K2203/0769 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49222 ,  Y10T29/4981 ,  H01L2924/00

Abstract: A method and apparatus are provided for connecting area grid array semiconductor chips (30) to a printed wire board (40). A compliant lead matrix (10) includes a carrier (12) and a plurality of conductive leads (14) arranged parallel to one another and secured relative to the carrier (12) in the form of a matrix. The method includes orienting a first side (16) of the lead matrix (10) to be aligned with a reciprocal matrix of conductive surface pads (36) on the area grid array semiconductor chip (30). First ends (20) of the leads are electrically connected to the conductive surface pads (36) of the area grid array chip (30). The second side (18) of the lead matrix (10) is oriented to be aligned with a reciprocal matrix of conductive surface pads (46) on a printed wire board (40). Second ends (22) of the leads (14) of the lead matrix (10) are electrically connected to the conductive surface pads (46) of the printed wire board (40) thereby establishing an electrical connection between the area grid array chip (30) and the printed wire board (40).

Abstract translation: 提供了一种用于将区域阵列半导体芯片（30）连接到印刷线路板（40）的方法和装置。 柔性引线矩阵（10）包括载体（12）和彼此平行布置并以矩阵的形式相对于载体（12）固定的多个导电引线（14）。 该方法包括将引线矩阵（10）的第一侧（16）定向成与区域栅格阵列半导体芯片（30）上的导电表面焊盘（36）的倒数矩阵对准。 引线的第一端（20）电连接到区域格栅阵列芯片（30）的导电表面焊盘（36）。 引线矩阵（10）的第二面（18）被定向成与印刷线路板（40）上的导电表面焊盘（46）的倒数矩阵对齐。 引线矩阵（10）的引线（14）的第二端（22）电连接到印刷线路板（40）的导电表面焊盘（46），由此在区域格栅阵列芯片（30）之间建立电连接 ）和印刷线路板（40）。

公开(公告)号：WO1996015459A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014885

申请日：1995-11-15

Applicant: FORMFACTOR, INC.

Inventor： FORMFACTOR, INC. ,  KHANDROS, Igor, Y. ,  MATHIEU, Gaetan, L. ,  ELDRIDGE, Benjamin, N. ,  GRUBE, Gary, W.

IPC: G01R01/073

CPC classification number: H05K7/1069 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/0483 ,  G01R31/2863 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/67138 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45644 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48844 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/48744 ,  H01L2924/20751 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/20754

Abstract: Resilient contact structures (430) are mounted directly to bond pads (410) on semiconductor dies (402a, 402b), prior to the dies (402a, 402b) being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies (402a, 402b) to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies (702, 704) with a circuit board (710) or the like having a plurality of terminals (712) disposed on a surface thereof. Subsequently, the semiconductor dies (402a, 402b) may be singulated from the semiconductor wafer, whereupon the same resilient contact structures (430) can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements (430) of the present invention as the resilient contact structures, burn-in (792) can be performed at temperatures of at least 150 DEG C, and can be completed in less than 60 minutes.

Abstract translation: 在将模具（402a，402b）与半导体晶片分离（分离）之前，将弹性接触结构（430）直接安装在半导体管芯（402a，402b）上的接合焊盘（410）上。 这使得半导体管芯（402a，402b）能够通过用具有多个端子的电路板（710）等连接到半导体管芯（702,704）来实现（例如，测试和/或烧入）半导体管芯（402a，402b） （712）设置在其表面上。 随后，半导体管芯（402a，402b）可以从半导体晶片分离，于是可以使用相同的弹性接触结构（430）来实现半导体管芯和其它电子部件（例如布线基板，半导体封装， 等等。）。 使用本发明的全金属复合互连元件（430）作为弹性接触结构，老化（792）可以在至少150℃的温度下进行，并且可以在少于60分钟内完成。

公开(公告)号：WO2008083250A3

公开(公告)日：2008-08-21

申请号：PCT/US2007088992

申请日：2007-12-27

Applicant: TEXAS INSTRUMENTS INC ,  STIBOREK LEON

Inventor： STIBOREK LEON

IPC: H01R13/02 ,  H01L21/48 ,  H01R12/00 ,  H05K1/00

CPC classification number: H05K3/3436 ,  H01L21/4853 ,  H01L23/49811 ,  H01L2223/6622 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/0219 ,  H05K3/4015 ,  H05K2201/09809 ,  H05K2201/10946 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2224/0401

Abstract: A contact grid array interconnect (100) element for mounting an IC package (130) to a substrate. The interconnect comprises an insulating stand-off post (110) having opposing ends. An electrically conductive core (105) is embedded in and traverses the post. Conductive endplates (125, 127) are located on the opposing ends (117, 120) of the post and contact the core.

Abstract translation: 一种用于将IC封装（130）安装到衬底的接触栅极阵列互连（100）元件。 互连包括具有相对端的绝缘支座（110）。 导电芯（105）嵌入并穿过柱。 导电端板（125,127）位于柱的相对端（117,120）上并与芯接触。

公开(公告)号：WO2005119849A1

公开(公告)日：2005-12-15

申请号：PCT/US2005/018946

申请日：2005-05-27

Applicant: MOLEX INCORPORATED

Inventor： NODA, Atsuhito ,  HOSHIKAWA, Shigeyuki ,  IKEDA, Hiroshi

IPC: H01R4/02

CPC classification number: H01R4/028 ,  H01L23/49811 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81012 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01R12/52 ,  H01R12/57 ,  H01R12/714 ,  H01R13/2407 ,  H01R13/2464 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/10265 ,  H05K2201/10719 ,  H05K2201/10946 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: Multiple small conductive and flexible hollow rings (10), each of which is made from a pliable material, provide a flexible connection medium for use between a substrate (23, 80, 82) and a microelectronic device package (88). Each ring is formed to have at least one protuberance (20) on the a ring's exterior surface. The protuberance has an apex (22) or point, which when placed against a surface, will scrub or scrape the surface as the ring is compressed by a force acting on the ring radially. By scrubbing a contact surface with the apex, surface contaminants and layered material that might interfere with electrical signals can be removed.

Abstract translation: 由柔韧材料制成的多个小导电和柔性中空环（10）提供用于衬底（23,80,82）和微电子器件封装（88）之间的柔性连接介质。 每个环形成为在环的外表面上具有至少一个突起（20）。 突起具有顶点（22）或点，当放置在表面上时，当环被径向作用在环上的力压缩时，将擦拭或刮擦表面。 通过用顶点擦拭接触表面，可以去除可能干扰电信号的表面污染物和分层材料。

公开(公告)号：WO00001208A1

公开(公告)日：2000-01-06

申请号：PCT/US1999/014924

申请日：1999-06-30

IPC: H05K1/18 ,  B23K1/00 ,  B23K20/00 ,  C23C18/16 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/01 ,  G01R31/28 ,  H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/603 ,  H01L21/66 ,  H01L23/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/32 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H05K1/14 ,  H05K3/20 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40

CPC classification number: H01L25/16 ,  B23K1/0016 ,  B23K20/004 ,  B23K2201/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07378 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19043 ,  H05K1/141 ,  H05K3/20 ,  H05K3/325 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/09472 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. A securing device such as a housing positions the electronic component securely to the socket substrate. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract translation: 提供产品和组件用于可插拔地接收从电子部件（例如半导体器件）延伸的细长互连元件，例如弹簧接触元件。 插座基板设置有用于接收从电子部件延伸的细长互连元件的端部的捕获垫。 公开了各种捕获垫结构。 诸如壳体的固定装置将电子部件牢固地定位到插座基板。 通过邻近插座基板表面的导电迹线提供与外部设备的连接。 插座基板可以由支撑基板支撑。 在特别优选的实施例中，捕获垫直接形成在诸如印刷电路板的主要基底上。

公开(公告)号：WO9737373A3

公开(公告)日：1997-11-27

申请号：PCT/US9704911

申请日：1997-03-27

Applicant: CERIDIAN CORP

Inventor： PAI DEEPAK KESHAV

IPC: H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H01L

CPC classification number: H05K3/303 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/3426 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10946 ,  H05K2203/0769 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49222 ,  Y10T29/4981 ,  H01L2924/00

Abstract: A method and apparatus are provided for connecting area grid array semiconductor chips (30) to a printed wire board (40). A compliant lead matrix (10) includes a carrier (12) and a plurality of conductive leads (14) arranged parallel to one another and secured relative to the carrier (12) in the form of a matrix. The method includes orienting a first side (16) of the lead matrix (10) to be aligned with a reciprocal matrix of conductive surface pads (36) on the area grid array semiconductor chip (30). First ends (20) of the leads are electrically connected to the conductive surface pads (36) of the area grid array chip (30). The second side (18) of the lead matrix (10) is oriented to be aligned with a reciprocal matrix of conductive surface pads (46) on a printed wire board (40). Second ends (22) of the leads (14) of the lead matrix (10) are electrically connected to the conductive surface pads (46) of the printed wire board (40) thereby establishing an electrical connection between the area grid array chip (30) and the printed wire board (40).

公开(公告)号：WO1993007657A1

公开(公告)日：1993-04-15

申请号：PCT/US1992008320

申请日：1992-09-30

Applicant: CERIDIAN CORPORATION

Inventor： CERIDIAN CORPORATION ,  PAI, Deepak, Keshav ,  KRINKE, Terrence, Albert

IPC: H01R09/00

CPC classification number: H01R12/57 ,  H01F2027/295 ,  H01L23/49811 ,  H01L23/49861 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/3426 ,  H05K3/36 ,  H05K13/0092 ,  H05K13/0465 ,  H05K2201/10727 ,  H05K2201/10757 ,  H05K2201/10924 ,  H05K2201/10946 ,  H05K2201/10984 ,  H05K2203/107 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A curved lead (14) provides a mechanical and electrical connection between a board contact (21) on a circuit board (20) and a chip contact (16) associated with a circuit chip (18). The chip (18) can be mounted to the circuit board (20), to a chip carrier (12) or to a multiple-chip module (90). The curved lead (14) is substantially entirely plated with solder and is formed of a single piece of conductive material (56). The curved lead (14) has a first surface (58) for connection to the chip contact (16) and a second surface (60), generally parallel to the first surface (58), for connection to the board contact (21). The first and second surfaces (58, 60) are connected by at least one curved portion and are arranged to mount the circuit chip (18) to the circuit board (20) with the solder in a compliant, generally parallel arrangement substantially free of stress.

Abstract translation: 弯曲引线（14）提供在电路板（20）上的电路板触点（21）与与电路芯片（18）相关联的芯片触点（16）之间的机械和电连接。 芯片（18）可以安装到电路板（20），芯片载体（12）或多芯片模块（90）。 弯曲引线（14）基本上完全用焊料电镀并且由单片导电材料（56）形成。 弯曲引线（14）具有用于连接到芯片触头（16）的第一表面（58）和大致平行于第一表面（58）的第二表面（60），用于连接到板触点（21）。 第一和第二表面（58,60）通过至少一个弯曲部分连接并被布置成将电路芯片（18）安装到电路板（20）上，其中焊料是基本上没有应力的顺从的大致平行布置 。

公开(公告)号：WO1990011629A1

公开(公告)日：1990-10-04

申请号：PCT/US1989001401

申请日：1989-04-03

Applicant: CRAY RESEARCH, INC.

Inventor： CRAY RESEARCH, INC. ,  KRAJEWSKI, Nicholas, J. ,  JOHNSON, David, J. ,  KUNSTMANN, Arthur, O.

IPC: H01R04/18

CPC classification number: H01L24/16 ,  C22F1/006 ,  H01L21/4853 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4943 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01204 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3011 ,  H01R4/01 ,  H01R12/523 ,  H05K3/308 ,  H05K3/328 ,  H05K3/36 ,  H05K3/368 ,  H05K2201/096 ,  H05K2201/1059 ,  H05K2201/10825 ,  H05K2201/10909 ,  H05K2201/10946 ,  H05K2203/0495 ,  Y10T29/49126 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/01004 ,  H01L2924/013

Abstract: A method and apparatus for interconnecting circuit board assemblies using memory metal wires mechanically inserted into through-plated holes. The invention has its application in the interconnection of stacked circuit board assemblies where kinked memory metal wires are stretched so the wires are substantially straight; inserted into axially aligned through-plated holes of circuit boards; and released so that the memory metal wires reform their original kinked shaped within the through-plated holes, forming an electrical connection between the circuit boards. Memory metal alloys are used in the construction of the kinked memory metal wires to take advantage of the pseudoelastic behavior of the alloys in the austenitic phase below the forming temperature range.

Abstract translation: 一种使用机械地插入通孔的存储金属线互连电路板组件的方法和装置。 本发明适用于堆叠电路板组件的互连，其中扭曲的存储金属线被拉伸，使得电线基本上是直的; 插入到电路板的轴向对齐的通孔中; 并释放，使得记忆金属线在穿透孔内改造其原来的扭结形状，在电路板之间形成电连接。 记忆金属合金用于扭结记忆金属丝的构造，以利用低于成形温度范围的奥氏体相中合金的假弹性行为。