公开(公告)号：JPH07220500A

公开(公告)日：1995-08-18

申请号：JP1166395

申请日：1995-01-27

Applicant: ST MICROELECTRONICS SRL

Inventor： OLIVO MARCO ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C16/06

Abstract: PURPOSE: To execute a test faster by excluding an internal state machine and directly programming a cell matrix to testify that the program is correct. CONSTITUTION: A test circuit 10 receives a test mode active signal from an address bus 2 and a data bus 3, the positions of switches I1 to 3 are switched. The switch I1 is switched to a second circuit 8 (programming circuit) connecting a signal WEN to a memory matrix. The switch I2 is switched to a first circuit 6 (generator) connecting a signal CEN to a circuit 2 and a word line. The switch 3 directly input a signal OPE to the circuit 6 and an output buffer circuit 7. As the result of this, the internal state machine is excluded and addresses can freely be used. Then a new test method programming a desired cell through the use of a control signal with a new meaning and testifying that the program is correct is obtained.

公开(公告)号：JPH07141894A

公开(公告)日：1995-06-02

申请号：JP13909694

申请日：1994-06-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F12/16 ,  G11C5/14 ,  G11C16/06 ,  G11C17/00

Abstract: PURPOSE: To prevent the failure of a memory by providing a control means to disable a comparator operation and turn on a switch when a first and a second power supply voltages are different from a prescribed threshold value by a certain value. CONSTITUTION: A threshold voltage for a PMOS transistor is expressed as VTH, a programming voltage as VPP, and a reference voltage as VREF. When VCC

公开(公告)号：JPH07141320A

公开(公告)日：1995-06-02

申请号：JP13909794

申请日：1994-06-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G11C17/00 ,  G06F15/78 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/48 ,  G11C29/50 ,  G11C16/06

Abstract: PURPOSE: To directly read the current of the integrated memory cells of a microcontroller by supplying a low voltage to the programming voltage supply line of a memory array, performing the write operation of the prescribed cell of the memory array and measuring the current flowing to the cell. CONSTITUTION: A node 19 is connected through a voltage supply line 16 and a switch 17 composed of an MOS transistor to a pin 18 supplied with a programming voltage Vpp. A programmable voltage source 30 and an ammeter or other current measuring element 31 are present at the outside of this microcontroller 1 and connected to the pin 18. By writing the read bit of a data cell or a reference cell in the cells 23 and 27 of a control register, selecting a prescribed pair of the cells by a word line and a data input bus, applying 1V to a programming pin 18 and issuing a write instruction (thus generating a high logic level in a write enable line W-EN and turning ON the switch 17), the cell is measured.

公开(公告)号：JPH07106604A

公开(公告)日：1995-04-21

申请号：JP20366994

申请日：1994-08-29

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: PURPOSE: To manufacture an integrated voltage control/stabilizing element having stable clamp voltage without additionally providing a manufacturing process in a flash EEPROM memory device. CONSTITUTION: This manufacturing method contains a process with which an N-type low doped well 2 is formed in a single crystal silicon substrate 1, a process with which an active region 4 is formed on the surface of the N-type well 2, a process with which a thin gate oxide layer is grown on the active region 4, and a process with which an N-type region 6 is formed by implanting the first high dosage of N-type dopant into the N-type well 2. Also, a process with which an N contact region 7 is obtained against both of the N-type well 2 and the N-type region 6 by implanting the N-type dopant of the second high dose higher than the first high dose, and a process with which a P region 8 is formed by implanting the P-type dopant of the third high dose, which is higher than the first high dose, into the N-type region 6, are provided.

公开(公告)号：JPH0755880A

公开(公告)日：1995-03-03

申请号：JP4408194

申请日：1994-03-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PEREGO ROMANO

IPC: G01R1/073 ,  G01R1/04 ,  G01R31/26 ,  H01L21/66 ,  H05K7/10

Abstract: PURPOSE: To enable juxtaposition of detecting forcing contacts making a pair of first and second electrical contact elements placed on a back plate form the Kelvin electric contacts of a semiconductor device by combining with an electrical contact element. CONSTITUTION: The contactor 1 has a plate 2 and a back plate 3 and is made from an electrically insulating material. First electrical contact element 8 is mounted on the plate 2, installed on arrays along two sides of a housing, and individually corresponds to the lead wires L of a semiconductor device D to be tested. Also, the element 8 is spring-loaded by the plate 2 by means of its own arched part and is biased toward the lead wire L of the device D placed within the housing. Second electrical contact element 10 is mounted on the plate 2 and placed near the element 8. The element 8 combine with the element 10 and an electrical connecting element 12 to form Kelvin type contacts. The elements 8 work as forcing contacts, and the elements 10 as detecting contacts.

公开(公告)号：JPH0750398A

公开(公告)日：1995-02-21

申请号：JP4720994

申请日：1994-03-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

Abstract: PURPOSE: To prevent the occurrences of stress in the drain terminal of an unselected memory cell in a selected bit line by biasing a positive voltage with respect to the drain terminal of the unselected memory cell for a substrate region and by making the source terminal remain floating. CONSTITUTION: This memory array is provided with a drain region 29 arranged into rows and columns and connected to each of bit lines BL, a source region 30 connected to each source line 24, a control gate region connected to each word line WL, and a large number of memory cells 21 each having a substrate region 28 housing the drain and source regions. A drain terminal of an unselected memory cell, which is connected to a selected bit line during a reading step but not connected to the selected word line and is not connected to the source terminal of the selected memory cell, is biased with a positive voltage with respect to the substrate region 28. The source terminal is kept floating.

公开(公告)号：JPH0750343A

公开(公告)日：1995-02-21

申请号：JP8961594

申请日：1994-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： JIYANNI FUORETSUTO ,  RAFUAERU FUSHIERO ,  SHIRUBIA RESUMA ,  MIKERU TARIERUCHIYO ,  RUIJI RICHIYARUDEI

IPC: H01L21/82 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L27/04

Abstract: PURPOSE: To provide a total integrated-circuit architecture related to a module integrated circuit which is advantageous in manufacture of large scale integrated circuit for digital data processing. CONSTITUTION: This integrated circuit having a large number of functional modules (M0, M1) equivalent to each other, having vertically-aligned functional elements (FF 1 to FF 3, +/-), and paths (gnd, vdd bus 1 to bus 8, vrt 1 to vrt 2) for power supply, control and interconnection, which extend on a substrate at various voltage levels. Power connection paths (gnd, vdd) horizontally extend across the respective modulus, and control parts (vrt 1-2) vertically extend across the functional elements of the adjacent modules. The element interconnection path within one module is formed by a horizontal section and a vertical section, which is particularly advatageous in the occupied region and applicable to a CAD design system.

公开(公告)号：JPH0745728A

公开(公告)日：1995-02-14

申请号：JP2054894

申请日：1994-02-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE

IPC: G11C5/00 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To prevent the control gate region of each cell from reaching a potential for damaging a tunnel oxide layer by providing a diode between the control gate region of a memory cell and a substrate. CONSTITUTION: In a flash EEPROM memory array, a cell 1 is arranged in columns and rows and the array has a control gate region 7 that is connected to word lines WL0-WL2 for determining the column of the array, a drain region that is connected to bit lines BL0-BL3 for determining the row of the array, and a source region that is connected to a source line SL. Then, a diode D is inserted between the control gate region 7 of the cell 1 and the substrate 2, and the control gate region 7 is closed to prevent an electric charge from passing, when an operation potential is brought about. When a potential that is lower than a breakdown potential that is high but is divided by a coupling coefficient is reached, the control gate region 7 is open-circuited and passes an electric charge.

公开(公告)号：JPH077140A

公开(公告)日：1995-01-10

申请号：JP27248493

申请日：1993-10-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  RAVAZZI LEONARDO

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

Abstract: PURPOSE: To detect the presence of a defective cell by analyzing current-voltage characteristic by using a test equipment which is the same as a memory array to be evaluated, except when each cell is connected in parallel. CONSTITUTION: In a test equipment 10, to which access can be performed from the outside by single pads 15, 18, and 21, an electric stress is applied to the gate oxide layers of EPROM, EEPROM, and flash EEPROM memories, so that electrons can be extracted from the floating gate region of a deflective cell, and a threshold characteristic of the cell are changed, while the charge of a non-defective cell remains without being charged. Then, a voltage lower than the threshold is applied, and drain currents related to the presence of at least one defective cell in an equipment passing through the cell are measured. The measurement and analysis of the current-voltage characteristic are conducted for deciding the number of defective cells. Gate currents can be measured indirectly through the measurement of the drain and source currents of the cells, and the detection of the defective cells can be attained.

公开(公告)号：JPH06258384A

公开(公告)日：1994-09-16

申请号：JP24132193

申请日：1993-09-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PELLEGRINI FRANCO

IPC: G01R31/26 ,  G01R1/36 ,  G01R31/28 ,  H01L21/66

Abstract: PURPOSE: To perform a reliable precise test by providing a current sensor, and an electric resistance changing means to be integrated with it. CONSTITUTION: A metal strip 15 has a detecting resistor 6 having a resistance value RS formed in a part thereof, and is connected to the drain terminal of a transistor 2 and a first pad 17. A metal strip 18 is extended to form a detecting resistance 10 having a resistance value Rs1 , and ended in a second pad 19 to form an input terminal 13. The pad 19 is connected to the negative input of an arithmetic amplifier, and the positive input is connected to the strip 18 through a voltage source 7 having a voltage VR. The pad 19 is connected to a circuit element for carrying a variable current to the resistor 6 in a wafer test, a current ILI passing a transistor 2 is carried through the resistors 6, 10, and the interposing condition of limit loop is thus represented by the expression I. In a final test, a terminal 13 is floated, a current IL2 is carried only to the resistor 6, and the interposing condition of limit loop is thus represented by the expression II. The nominal currents measured in both the tests are determined by a magnification K represented by the expression III, and a high magnification can be also attained by the selection of Rs1 .