公开(公告)号：DE59902239D1

公开(公告)日：2002-09-05

申请号：DE59902239

申请日：1999-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NEUHOLD ERNST ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C11/22 ,  G06F11/20 ,  G11C29/00 ,  G11C29/04

Abstract: An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

公开(公告)号：DE10062570C1

公开(公告)日：2002-06-13

申请号：DE10062570

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR

IPC: G11C8/12 ,  G11C11/15 ,  G11C11/14

Abstract: The read and write control circuit has selection transistors provided for each bit line (BL) on both sides of each memory cell connected to respective pairs of read/write amplifiers (AMPH,AMPL) at the bit line ends, each having a current source and a current drain. The read/write amplifiers respond to a write signal, to provide a write current in one or other direction for write-in of a logic 0 or 1 for all bit lines selected by a column select signal applied to a column select line (CS), with read out of the logic 0 or 1 by application of a read signal to a selected memory cell. An Independent claim for a magnetoresistive memory is also included.

公开(公告)号：DE10055936A1

公开(公告)日：2002-05-23

申请号：DE10055936

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14 ,  G11C11/15

Abstract: The device has magnetic memory cells at intersections of a cell field with a matrix of row and column lines. In a write operation the magnetic fields generated by write currents in the lines add at an optional intersection to enable demagnetization of the local memory cell. The shape of the lines is optimized so that the magnetic field component in the plane of the cell field decreases rapidly with increasing distance from the intersection.

公开(公告)号：DE19841445C2

公开(公告)日：2002-04-25

申请号：DE19841445

申请日：1998-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWARIK OSKAR ,  HOFFMANN KURT ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

IPC: G11C16/06 ,  G11C8/10 ,  G11C11/407 ,  G11C16/08 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.

公开(公告)号：DE10054521A1

公开(公告)日：2002-02-14

申请号：DE10054521

申请日：2000-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

Abstract: A method for reading data from a memory arrangement (15-18) having several memory units (11-14), each of the latter having memory cells equipped with word- and bit-lines; the memory units have a word-line decoder (2) and a bit-line decoder (3). An address decoder (21) is connected to the word-line decoders (2) and to the bit-line decoders (3). Data is read out from the memory cells alternately from different memory units (11-14).

公开(公告)号：DE10019481C1

公开(公告)日：2001-11-29

申请号：DE10019481

申请日：2000-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.

公开(公告)号：DE102006011462B4

公开(公告)日：2008-07-10

申请号：DE102006011462

申请日：2006-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAW CORVIN ,  HOENIGSCHMID HEINZ ,  BRUCHHAUS RAINER

IPC: G11C13/02

公开(公告)号：DE50113958D1

公开(公告)日：2008-06-26

申请号：DE50113958

申请日：2001-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  ROEHR THOMAS DR

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: The method involves the use of a pre-charge step that coincides with each drive phase of a short circuit transistor and during which the selection transistors are blocked. After the selection of memory cells the drive phases of the corresp. short circuit transistors of the selected cells are terminated by a negative potential on the corresp. word line of each short circuit transistor.

公开(公告)号：DE102006008492A1

公开(公告)日：2007-08-30

申请号：DE102006008492

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAW CORVIN ,  HOENIGSCHMID HEINZ ,  DIMITROVA MILENA ,  ANGERBAUER MICHAEL

IPC: G11C13/02 ,  G11C7/12

Abstract: The storage circuit has a resistance memory cell (10) with a selection transistor (12) and a resistance memory element (11), which is switched into row. The resistance memory element is connected with a disk potential (Vpl). A control circuit is designed to steer the select transistor with the help of an activation signal. A pre-charge circuit (19) is coupled with a knot between the select transistor and the resistance memory element. An independent claim is also included for a method for operation of storage circuits.

公开(公告)号：DE102005061995A1

公开(公告)日：2007-06-28

申请号：DE102005061995

申请日：2005-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  DIMITROVA MILENA ,  LIAW CORVIN ,  ANGERBAUER MICHAEL

IPC: G11C13/02

Abstract: The circuit has a resistance memory unit (14) which is connected with a connection with a disc potential. A bit circuit (12) is connected with another connection of the resistance memory unit, and a programming circuit is formed to change resistance of the resistance memory unit. A discharge circuit (20) is formed to make possible a discharge current in or from the bit circuit to aid recharging of the bit circuit, where the recharging of the bit circuit is caused by changing the resistance of the resistance memory unit. An independent claim is also included for a method for operating a memory circuit.