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    72.
    发明专利
    未知

    公开(公告)号：DE10017368B4

    公开(公告)日：2005-12-15

    申请号：DE10017368

    申请日：2000-04-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

    IPC: G11C11/22 ,  G11C7/02 ,  G11C7/08 ,  G11C7/22

    Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the "pulsed plate concept". In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

    73.
    发明专利
    未知

    公开(公告)号：DE102005018344A1

    公开(公告)日：2005-12-01

    申请号：DE102005018344

    申请日：2005-04-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  HAPP THOMAS

    IPC: G02F1/153 ,  G11C13/02 ,  G11C16/00 ,  H01L23/525 ,  H01L27/24 ,  H01L29/02 ,  H01L45/00 ,  H01L47/00 ,  H03F3/45

    Abstract: A switching device to be reversibly switched between an electrically isolating off-state and an electrically conducting on-state for use in, e.g., a reconfigurable interconnect. The device includes two separate electrodes, one of which being a reactive metal electrode and the other one being an inert electrode, and a solid state electrolyte arranged between the electrodes and being capable of electrically isolating the electrodes to define the off-state. The reactive metal electrode and the solid state electrolyte also being capable of forming a redox-system having a minimum voltage (turn-on voltage) to start a redox-reaction, which results in generating metal ions that are released into the solid state electrolyte. The metal ions are reduced to increase a metal concentration within the solid state electrolyte, wherein an increase of the metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.

    2t2c signal margin test mode using different pre-charge levels for bl and /bl
    75.
    发明专利
    2t2c signal margin test mode using different pre-charge levels for bl and /bl 未知

    公开(公告)号：AU2003278684A8

    公开(公告)日：2004-06-15

    申请号：AU2003278684

    申请日：2003-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JOACHIM HANS-OLIVER ,  JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

    IPC: G11C29/50 ,  G11C29/00

    Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A potential is connected to the first bit line through a third transistor and changes a pre-charge signal level on the first bit line when the third transistor is turned on to reduce the differential read signal.

    78.
    发明专利
    未知

    公开(公告)号：DE59901953D1

    公开(公告)日：2002-08-08

    申请号：DE59901953

    申请日：1999-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS ,  KOWARIK OSKAR ,  HOFFMANN KURT

    IPC: G11C11/22 ,  G11C29/12

    Abstract: A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

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