公开(公告)号：DE102004061518A1

公开(公告)日：2006-06-29

申请号：DE102004061518

申请日：2004-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ILICALI GUERKAN ,  LANDGRAF ERHARD ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12

Abstract: The method involves producing an electrically conductive layer according to production of an insulating area at the insulating area and over a top surface. An auxiliary layer (40) is produced according to the production of the electrically conductive layer. The auxiliary layer covers a part of the electrically conductive layer and does not cover a part of the electrically conductive layer that is arranged over the top surface. An independent claim is also included for an integrated switching arrangement.

公开(公告)号：DE10320239A1

公开(公告)日：2004-12-02

申请号：DE10320239

申请日：2003-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUVKEN JOHANNES ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SPECHT MICHAEL ,  SCHLOESSER TILL ,  MANGER DIRK

IPC: H01L21/8238 ,  H01L21/8242 ,  H01L27/108

Abstract: A DRAM memory cell comprises a select transistor (200) on a semiconductor substrate with source/ drain electrodes (201,202), a channel layer (203), an isolated gate electrode, a memory capacitor (100) with two electrodes, one connected to the source/drain and a rear substrate electrode. The gate electrode surrounds opposite sides of the channel. An independent claim is also included for a production process for the above DRAM.

公开(公告)号：DE10248723A1

公开(公告)日：2004-05-06

申请号：DE10248723

申请日：2002-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  HARTWICH JESSICA ,  BREDERLOW RALF ,  PACHA CHRISTIAN

IPC: H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

公开(公告)号：DE10241945A1

公开(公告)日：2004-03-18

申请号：DE10241945

申请日：2002-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L29/78

Abstract: Production of a planar transistor comprises forming a semiconductor-on-isolator substrate having a support layer (101), a first insulating layer (102) and a semiconductor layer (105), forming a gate insulating layer (207) and a gate region on the substrate, forming a second insulating layer (104) and etching the isolator layer, semiconductor layer and substrate to define source/drain regions, forming a contact region between the transistor below the gate insulating layer and the source/drain regions, and forming source/drain connections. An Independent claim is also included for a planar transistor produced by the above process.

公开(公告)号：DE10233663A1

公开(公告)日：2004-02-19

申请号：DE10233663

申请日：2002-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DREESKORNFELD LARS ,  ROESNER WOLFGANG ,  HARTWICH JESSICA

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12

Abstract: Production of a SOI substrate comprises preparing a SOI substrate by: (a) embedding a trenched oxide layer (BOX) between a crystalline silicon layer and a silicon substrate (Si); (b) applying a hard mask layer on at least one region of the silicon layer; (c) forming a window in the hard mask layer to expose the silicon layer in the window region; (d) removing the silicon layer in the window region by dry etching from a first silicon layer thickness to a second silicon layer thickness; and (e) removing the silicon layer in the window region by local oxidation of the silicon and wet chemical etching of the silicon oxide formed to a third silicon layer thickness.

公开(公告)号：DE10227605A1

公开(公告)日：2004-01-15

申请号：DE10227605

申请日：2002-06-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  KRETZ JOHANNES

IPC: H01L21/8242 ,  H01L25/065 ,  H01L21/58 ,  H01L21/283 ,  H01L27/108 ,  H01L27/112

Abstract: A layer system comprises a substrate having a surface processed with a conductive metal structure and an opposite processed second surface. A second substrate is attached by a third surface to the first surface of the first substrate. An independent claim is also included for a process for producing the system above.

公开(公告)号：DE10223719C1

公开(公告)日：2003-11-27

申请号：DE10223719

申请日：2002-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN JOHANNES R ,  ROESNER WOLFGANG ,  HOFMANN FRANZ ,  KRETZ JOHANNES

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/822 ,  H01L21/98 ,  H01L25/065 ,  H01L27/06 ,  H01L21/58 ,  H01L27/12

Abstract: Layer arrangement comprises a first substrate (101) having a first main surface (102) containing a first thermally dissolvable delamination layer (103) produced by implanting hydrogen, and a second substrate (104) having a second main surface (105) containing a second thermally dissolvable delamination layer (106) made from porous silicon. The first main surface of the first substrate is fixed to the second main surface of the second substrate. The second thermally dissolvable delamination layer is more stable than the first layer. An Independent claim is also included for a process for the production of a layer arrangement.

公开(公告)号：DE10030391C2

公开(公告)日：2003-10-02

申请号：DE10030391

申请日：2000-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTWICH JESSICA ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/786 ,  H01L21/283

公开(公告)号：DE10158019C2

公开(公告)日：2003-09-18

申请号：DE10158019

申请日：2001-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  STAEDELE MARTIN ,  ROESNER WOLFGANG ,  HOFMANN FRANZ

IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

公开(公告)号：DE10132640A1

公开(公告)日：2003-01-23

申请号：DE10132640

申请日：2001-07-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  LUYKEN JOHANNES R ,  HARTWICH JESSICA ,  KRETZ JOHANNES

IPC: B82B1/00 ,  G11C11/21 ,  G11C13/02 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  H01L51/20

Abstract: The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.