公开(公告)号：KR1020130015859A

公开(公告)日：2013-02-14

申请号：KR1020110078154

申请日：2011-08-05

Applicant: 고려대학교 산학협력단

Inventor： 김철우 ,  김무영 ,  이호규

IPC: H03M1/12

CPC classification number: H03M1/38 ,  H03M1/122 ,  H03M1/14 ,  H03M2201/2233 ,  H03M2201/62

Abstract: PURPOSE: An analogue to digital converter is provided to tremendously reduce the amount of input capacitance by partially applying the algorithm of a pipeline ADC(Analogue to Digital Converter) to a successive approximation register ADC. CONSTITUTION: A first voltage input part(170) outputs a first voltage. A second voltage input part(180) outputs a second voltage. First and second sample holding parts(110,120) perform sample holding operations based on a first input voltage, a second input voltage, and a common voltage. A first capacitor array(150) is selectively connected to the output terminal of the first sample holding part. A second capacitor array(160) is selectively connected to the output terminal of the second sample holding part. A double comparison part(190) compares the output voltages of the first voltage input part, the second voltage input part, the first capacitor array, and the second capacitor array. An SAR(Successive Approximation Register) control part(200) generates a digital code for the input voltage. [Reference numerals] (190) Double comparison part; (200) SAR control part

Abstract translation: 目的：通过将流水线ADC（模数转换器）的算法部分应用于逐次逼近寄存器ADC，可提供模数转换器，以极大地减少输入电容量。 构成：第一电压输入部（170）输出第一电压。 第二电压输入部分（180）输出第二电压。 第一和第二样品保持部件（110,120）基于第一输入电压，第二输入电压和公共电压进行采样保持操作。 第一电容器阵列（150）选择性地连接到第一样品保持部分的输出端子。 第二电容器阵列（160）选择性地连接到第二样品保持部分的输出端子。 双重比较部分（190）比较第一电压输入部分，第二电压输入部分，第一电容器阵列和第二电容器阵列的输出电压。 SAR（连续近似寄存器）控制部分（200）产生用于输入电压的数字代码。 （附图标记）（190）双重比较部; （200）SAR控制部分

公开(公告)号：KR101200942B1

公开(公告)日：2012-11-13

申请号：KR1020110103277

申请日：2011-10-10

Applicant: 동국대학교 산학협력단

Inventor： 송민규 ,  김대윤 ,  김영훈 ,  최동귀

IPC: H03M1/12

CPC classification number: H03M1/141 ,  H03M1/121 ,  H03M2201/2216 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/93

Abstract: PURPOSE: An analog-digital converter and a method thereof are provided to increase accuracy by using folding and interpolation. CONSTITUTION: An upper signal processing part(120) generates an upper analog signal by amplifying an analog signal in a preset amplification ratio. A lower signal processing part(130) generates a lower analog signal by amplifying and folding the analog signal through an amplification line including an odd number of amplifiers. A comparison part(140) generates a comparison signal by comparing the upper analog signal and the lower analog signal according to a preset reference voltage. An encoding part(150) generates an upper digital signal by the upper analog signal and a lower digital signal by the lower analog signal according to the comparison signal. The encoding part generates an output signal by adding the upper digital signal and the lower digital signal. [Reference numerals] (110) Input part; (120) Upper signal processing part; (130) Lower signal processing part; (140) Comparison part; (150) Encoding part

Abstract translation: 目的：提供一种模拟数字转换器及其方法，以通过使用折叠和插值来提高精度。 构成：上信号处理部（120）通过以预设的放大率放大模拟信号来生成上模拟信号。 较低信号处理部分（130）通过包括奇数放大器的放大线放大和折叠模拟信号来产生较低的模拟信号。 比较部分（140）通过根据预设的参考电压比较上模拟信号和下模拟信号来产生比较信号。 编码部分（150）根据比较信号通过上模拟信号和较低数字信号通过较低模拟信号产生上数字信号。 编码部分通过将上数字信号和下数字信号相加来产生输出信号。 （附图标记）（110）输入部; （120）上信号处理部分; （130）下信号处理部分; （140）比较部分; （150）编码部分

公开(公告)号：KR1020120114103A

公开(公告)日：2012-10-16

申请号：KR1020110031886

申请日：2011-04-06

Applicant: 한국과학기술원

Inventor： 류승탁 ,  김시내

IPC: H03M1/66

CPC classification number: H03M1/0607 ,  H03M1/66 ,  H03M2201/62 ,  H03M2201/6372 ,  H03M2201/718 ,  H03M2201/932

Abstract: PURPOSE: A digital to analog converter and an automatic correction method are provided to stably maintain dynamical linearity even in a high frequency band by minimizing a parasitic capacitance of a unit current source output terminal. CONSTITUTION: A laminated unit cell(310) comprises a current source transistor(311), a cascode transistor(312), a differential switch(313), and a switch driver(314) which are successively laminated. A plurality of laminated unit cells can be arranged in parallel. The plurality of laminated unit cells can be grouped in a bit unit having a binary weighted value. Each layer is laminated in a laminating structure. A parasitic capacitance can be reduced by a signal connection line.

Abstract translation: 目的：提供数模转换器和自动校正方法，通过最小化单位电流源输出端子的寄生电容，即使在高频带也可稳定地保持动态线性。 构成：叠层单元（310）包括依次层叠的电流源晶体管（311），共源共栅晶体管（312），差分开关（313）和开关驱动器（314）。 多个层叠单元电池可以并列布置。 可以将多个层叠单位电池分组成具有二进制加权值的位单元。 每层层叠在层压结构中。 通过信号连接线可以减小寄生电容。

公开(公告)号：KR101160961B1

公开(公告)日：2012-06-29

申请号：KR1020110038934

申请日：2011-04-26

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  명성민 ,  김효진

IPC: H03M1/12

CPC classification number: H03M1/122 ,  H03M1/002 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/62

Abstract: PURPOSE: An ADC(Analog to Digital Converter) sharing amplifiers between two channels is provided to additionally reduce the number of pre-amplifiers by 50% by applying an interpolation method to flash ADCs. CONSTITUTION: An ADC(Analog to Digital Converter) includes a SHA(Sample-and-Hold Amplifier)(110), a MDAC1(Multiplying Digital to Analog Converter)(120), a MDAC2(130), a FLASH1(140), a FLASH2(150), and a FLASH3(160). The ADC includes an on-chip reference current and voltage generator(170), a digital correction circuit(180) including a divider, and a clock generator(190). Input terminals of the SHA, the MDAC1, and the MDAC2 are composed of two channels. Two channels share only one amplifier. The FLASH1, the FLASH2, and the FLASH3 are composed of a pre-amplifier and a latch. The FLASH1, the FLASH2, and the FLASH3 reduce the number of pre-amplifiers by 50% to consecutively process signals outputted from the SHA, the MDAC1, and the MDAC2 by sharing one pre-amplifier having a DDA(Differential Difference Amplifier) structure.

Abstract translation: 目的：提供两个通道之间的ADC（模/数转换器）共享放大器，通过对闪存ADC应用内插方法，将前置放大器的数量额外减少50％。 组件：ADC（模数转换器）包括一个SHA（采样保持放大器）（110），一个MDAC1（乘法数模转换器）（120），一个MDAC2（130），一个FLASH1（140） FLASH2（150）和FLASH3（160）。 ADC包括片上参考电流和电压发生器（170），包括分频器的数字校正电路（180）和时钟发生器（190）。 SHA，MDAC1和MDAC2的输入端子由两个通道组成。 两个通道只共享一个放大器。 FLASH1，FLASH2和FLASH3由前置放大器和锁存器组成。 FLASH1，FLASH2和FLASH3通过共享一个具有DDA（差分放大器）结构的前置放大器，将前置放大器的数量减少了50％，以连续地处理从SHA，MDAC1和MDAC2输出的信号。

公开(公告)号：KR1020120024278A

公开(公告)日：2012-03-14

申请号：KR1020100087100

申请日：2010-09-06

Applicant: 서강대학교산학협력단

Inventor： 이승훈

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/002 ,  H03M1/1205 ,  H03M1/18 ,  H03M2201/2216 ,  H03M2201/62

Abstract: PURPOSE: An analog-to-digital converter using a range-scaling method is provided to reduce the number of a reference voltage driving circuit to the half without additional correction on reference voltage using the single reference voltage. CONSTITUTION: Range scaling on the input analog signal of an ADC(Analog-to-Digital Converter) of a pipeline structure is operated using only single reference voltage. An SHA(Sample-and-Hold Amplifier) of an input terminal of the ADC is removed from the input terminal of the ADC. The input analog signal is directly applied on the sampling capacitor of the FLASH1 ADC of input terminal and the MDAC1 of the input terminal. The sampling switch of the FLASH1 ADC and MDAC1 comprise a gate - bootstrapping circuit. The FLASH1 ADC is formed using only a plurality of latches.

Abstract translation: 目的：提供使用范围缩放方法的模数转换器，以将参考电压驱动电路的数量减少到一半，而无需使用单个参考电压对参考电压进行附加校正。 规定：管道结构的ADC（模数转换器）的输入模拟信号的范围缩放仅使用单个参考电压进行操作。 ADC的输入端子的SHA（采样保持放大器）从ADC的输入端子被去除。 输入模拟信号直接施加在输入端子FLASH1 ADC的采样电容和输入端子的MDAC1上。 FLASH1 ADC和MDAC1的采样开关包括一个门自举电路。 FLASH1 ADC仅使用多个锁存器形成。

公开(公告)号：KR101111638B1

公开(公告)日：2012-02-14

申请号：KR1020110056421

申请日：2011-06-10

Applicant: 동국대학교 산학협력단

Inventor： 송민규 ,  조규익 ,  김대윤

IPC: H03M1/12 ,  H04N5/3745

CPC classification number: H03M1/56 ,  H03M1/002 ,  H03M1/12 ,  H03M3/02 ,  H03M2201/2311 ,  H03M2201/62 ,  H04N5/3745

Abstract: PURPOSE: An analog-to-digital converter using correlated double sampling and an analog-to-digital converting method using the same are provided to reduce switching noise and power consumption by satisfying the number of bits to count the dissemination of reset signals. CONSTITUTION: A CMOS image sensor comprises a pixel array(1), a comparator(2), a CDS processing unit(3), an N-bit counter(6), and a latch unit(7). The CMOS image sensor comprises a vertical scanning circuit(8), a horizontal scan circuit(9), a lamp signal generator(10), an output circuit(11), and a control signal generating unit(12). The CDS processing unit comprises a CDS counter(4) and an and-logic(5) The control signal generating unit creates signals to control a vertical scanning circuit, a horizontal scanning circuit, a CDS processing unit, an N bit counter.

Abstract translation: 目的：提供使用相关双采样的模数转换器和使用其的模数转换方法，以通过满足计数复位信号传播的位数来减少开关噪声和功耗。 构成：CMOS图像传感器包括像素阵列（1），比较器（2），CDS处理单元（3），N位计数器（6）和锁存单元（7）。 CMOS图像传感器包括垂直扫描电路（8），水平扫描电路（9），灯信号发生器（10），输出电路（11）和控制信号生成单元（12）。 CDS处理单元包括CDS计数器（4）和逻辑电路（5）。控制信号产生单元产生信号以控制垂直扫描电路，水平扫描电路，CDS处理单元，N位计数器。

公开(公告)号：KR1020110011532A

公开(公告)日：2011-02-08

申请号：KR1020100056911

申请日：2010-06-16

Applicant: 한국전자통신연구원

Inventor： 김이경 ,  조민형 ,  권종기

IPC: H03M3/02 ,  H03M1/66 ,  H03G3/20

CPC classification number: H03M3/32 ,  H03M3/39 ,  H03M2201/62 ,  H03M2201/932

Abstract: PURPOSE: An active type RC integrator and a continuous time sigma-delta modulator are provided to improve the gain of an active type RC integrator by turning on a switch. CONSTITUTION: A first base resistor(RBASE1) is connected between a first input node and the positive input terminal of an amplifier. A second base resistor(RBASE2) is connected between a second input node and the negative input terminal of the amplifier. A first resistor part(1) is connected between the second input node and the positive input terminal of the amplifier. A second resistor part(2) is connected between the first input node and the negative input terminal of the amplifier. A first switch(SWDUM1) switches on and off the first base resistor. A second switch(SWDUM2) switches on and off the second base resistor. The gain of an input signal is controlled according to the input resistance varied by the first resistor part and the second resistor part.

Abstract translation: 目的：提供有源型RC积分器和连续时间Σ-Δ调制器，通过开启开关来提高有源型RC积分器的增益。 构成：第一个基极电阻（RBASE1）连接在放大器的第一个输入节点和正极输入端子之间。 第二基极电阻（RBASE2）连接在放大器的第二输入节点和负输入端之间。 第一电阻器部分（1）连接在第二输入节点和放大器的正输入端之间。 第二电阻器部分（2）连接在放大器的第一输入节点和负输入端之间。 第一开关（SWDUM1）打开和关闭第一个基极电阻。 第二个开关（SWDUM2）打开和关闭第二个基极电阻。 根据由第一电阻器部件和第二电阻器部件变化的输入电阻来控制输入信号的增益。

公开(公告)号：KR1020100123103A

公开(公告)日：2010-11-24

申请号：KR1020090042136

申请日：2009-05-14

Applicant: 주식회사 실리콘웍스

Inventor： 김기덕 ,  조규형 ,  전용준 ,  전진용 ,  정승철 ,  이성우

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/66 ,  H03M1/06 ,  H03M2201/3194 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/814

Abstract: PURPOSE: By it partials, medially eliminating error toward the input of digital data the digital to analog converter enhances the accuracy of the digital to analog converter. CONSTITUTION: It distributes to the before distribution class field of the plurality having the size of the reference current decision by discussion search the reference current which the electric current distribution part(20) is provided from the reference current route of supply source. According to the rotating exchange part is the control signal, the route of the before distribution class field having the route of being exchanged as described above is re-exchanged.

Abstract translation: 目的：通过内部消除数字数据输入的错误，数模转换器提高了数模转换器的精度。 构成：通过讨论从供应源的参考电流路径提供电流分配部（20）的参考电流，分配到具有参考电流决定大小的多个的前分发类场中。 根据旋转交换部分是控制信号，重新交换具有如上所述交换路线的分配前场的路线。

公开(公告)号：KR1020100027278A

公开(公告)日：2010-03-11

申请号：KR1020080086126

申请日：2008-09-02

Applicant: 충북대학교 산학협력단

Inventor： 김남수 ,  최지원

IPC: H03M1/12 ,  H03M1/16

CPC classification number: H03M1/16 ,  H03M1/002 ,  H03M1/18 ,  H03M2201/62 ,  H03M2201/814

Abstract: PURPOSE: An analog to digital converter using threshold voltage variation is provided to simplify a configuration of a circuit by performing a comparison operation with a simple structure. CONSTITUTION: A switching inverter array(120) is comprised of a plurality of CMOS inverters. The switching inverter array receives an analog input voltage as an input signal. An encoder(150) generates a digital signal by encoding the output signals of the CMOS inverters. Each CMOS inverter has a different switching threshold voltage. The CMOS inverters is comprised of a PMOS transistor and an NMOS transistor including a gate insulation layer. The PMOS transistor and the NMOS transistor have different thicknesses according to each CMOS inverter.

Abstract translation: 目的：提供使用阈值电压变化的模数转换器，通过简单的结构执行比较操作来简化电路的配置。 构成：开关逆变器阵列（120）由多个CMOS反相器构成。 开关逆变器阵列接收模拟输入电压作为输入信号。 编码器（150）通过对CMOS反相器的输出信号进行编码来产生数字信号。 每个CMOS反相器具有不同的开关阈值电压。 CMOS反相器由PMOS晶体管和包括栅极绝缘层的NMOS晶体管组成。 根据每个CMOS反相器，PMOS晶体管和NMOS晶体管具有不同的厚度。

公开(公告)号：KR1020090116942A

公开(公告)日：2009-11-12

申请号：KR1020080042774

申请日：2008-05-08

Applicant: 연세대학교 산학협력단 ,  동국대학교 산학협력단

Inventor： 김재석 ,  송민규 ,  정민호 ,  문준호 ,  이두복

IPC: H03M1/12

CPC classification number: H03M1/368 ,  H03M1/002 ,  H03M1/121 ,  H03M2201/2208 ,  H03M2201/62 ,  H03M2201/93

Abstract: PURPOSE: A folding-interpolating analog to a digital converter using a less track-and-hold circuit is provided to reduce a circuit area and power consumption by connecting a track-and-hold circuit at the end of a folding block stage. CONSTITUTION: In a folding-interpolating analog to a digital converter using a less track-and-hold circuit, a preamplifier stage(210) amplifies an analog signal by using a plurality of reference voltages and produces a plurality of input signals. A folding block stage(230) folds the input signals according to a predetermined folding rate. The folding block stage produces a plurality of folding signals. The track-and-hold stage(250) is arranged at the backend of the folding block stage by receiving the outputs of the folding block stage. The track-and-hold stage track and holds the folding signals.

Abstract translation: 目的：提供使用较少轨道和保持电路的数字转换器的折叠内插模拟，以通过在折叠块级结束时连接跟踪和保持电路来减少电路面积和功耗。 构成：在使用较少轨道和保持电路的数字转换器的折叠内插模拟中，前置放大器级（210）通过使用多个参考电压来放大模拟信号并产生多个输入信号。 折叠台阶（230）根据预定的折叠速率折叠输入信号。 折叠台阶产生多个折叠信号。 跟踪保持阶段（250）通过接收折叠块阶段的输出而被布置在折叠块阶段的后端。 跟踪和保持阶段跟踪并保存折叠信号。