公开(公告)号：WO2006063277A2

公开(公告)日：2006-06-15

申请号：PCT/US2005/044704

申请日：2005-12-09

Applicant: INTEL CORPORATION ,  FANEUF, Barrett ,  ALDRIDGE, Tomm

Inventor： FANEUF, Barrett ,  ALDRIDGE, Tomm

CPC classification number: G06Q30/0601 ,  F28D15/0266 ,  H01L23/427 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/141 ,  H05K7/1092 ,  H05K7/20309 ,  H05K2201/064 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/00

Abstract: According to some embodiments, a cooling device may comprise first and second contact surfaces to transfer heat to a cooling medium. The cooling device may further comprise, in some embodiments, a first electrical component coupled to transmit heat to the first contact surface and a second electrical component coupled to transmit heat to the second contact surface.

Abstract translation: 根据一些实施例，冷却装置可以包括将热量传递到冷却介质的第一和第二接触表面。 在一些实施例中，冷却装置还可以包括耦合以将热传递到第一接触表面的第一电气部件和耦合以将热传递到第二接触表面的第二电气部件。

公开(公告)号：WO2003090278A2

公开(公告)日：2003-10-30

申请号：PCT/US2003/009681

申请日：2003-03-27

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  CHIU, Chia-Pin ,  NAIR, Rajendran ,  LI, Yian-Liang

IPC: H01L23/367

CPC classification number: H01L23/4006 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4093 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K1/0204 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10477 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: The present invention describes a method and apparatus for mounting a microelectronic device parallel to a substrate with an interposer and two heat sinks, one on each side of the substrate.

Abstract translation: 本发明描述了一种用于利用中介层和两个散热片将平行于基板的微电子器件安装到基板的每一侧上的方法和设备。

公开(公告)号：WO03038865A2

公开(公告)日：2003-05-08

申请号：PCT/US0234923

申请日：2002-10-31

Applicant: VIRTIUM TECHNOLOGY INC

Inventor： NGUYEN CHINH ,  HOANG PHU ,  HOANG PHAN ,  LE ANDY

IPC: H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H01L

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/144 ,  H05K3/3421 ,  H05K3/3463 ,  H05K2201/0367 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10992 ,  H05K2203/043 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: In one embodiment of the invention, a stacking element includes a printed circuit board (PCB) and a plurality of solder bumps. The PCB has a top side and a bottom side. The top side is attached to first pins of a first device. The plurality of solder bumps are on the bottom side and attached to upper areas of second pins of a second device to provide electrical connections between the first pins and the second pins.

Abstract translation: 在本发明的一个实施例中，堆叠元件包括印刷电路板（PCB）和多个焊料凸块。 PCB具有顶侧和底侧。 顶侧连接到第一设备的第一个引脚。 多个焊料凸块位于底侧，并附接到第二器件的第二引脚的上部区域，以提供第一引脚和第二引脚之间的电连接。

公开(公告)号：WO00056130A1

公开(公告)日：2000-09-21

申请号：PCT/SE2000/000493

申请日：2000-03-13

IPC: H01L23/40 ,  H01L23/36 ,  H01L23/498 ,  H05K1/02 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H01L23/34

CPC classification number: H05K1/0209 ,  H01L23/36 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/141 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: The present invention relates to a method and to an arrangement for connecting a component, such as a chip (6), on a substrate (7) to a conductive surface of a carrier, such as an earth plane (10) on a printed circuit board (8) having a conductive layer (11) in a so-called compact design.

Abstract translation: 本发明涉及一种用于将基板（7）上的诸如芯片（6）的部件连接到诸如印刷电路上的接地平面（10）的载体的导电表面上的方法和装置， 板（8）具有所谓紧凑设计的导电层（11）。

公开(公告)号：WO1998010627A1

公开(公告)日：1998-03-12

申请号：PCT/IB1997000801

申请日：1997-07-01

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  DE SAMBER, Mark, André ,  VAN DE WALLE, Gerjan, Franciscus, Arthur

IPC: H05K01/18

CPC classification number: H05K3/3442 ,  H01G4/306 ,  H01L23/49805 ,  H01L2224/16 ,  H01L2224/32225 ,  H05K2201/10477 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49787 ,  Y10T29/49789

Abstract: The invention relates to an electric component (surface mountable component) which can be mounted on the surface of a printed circuit board, and to a method of manufacturing said component. Such a component comprises a thin, electroconductive layer or stack of layers which is provided with end contacts and arranged on a support of an electrically insulating material. In accordance with the invention, the dimension of the layer or stack of layers in at least one direction parallel to the surface of the support is smaller than the dimension of the support in said direction, while leaving portions of the surface of the support clear on at least two sides of the layer or stack of layers, and end contacts for the layer or stack of layers are situated on the surface portions of the support which are free of this layer or stack of layers, the thickness of said end contacts being larger than the thickness of the layer or stack of layers. The method in accordance with the invention enables small-size electric components to be manufactured in which the end contacts form a reliable electric connection with the electroconductive layer or stack of layers of the component.

Abstract translation: 本发明涉及一种可安装在印刷电路板的表面上的电气部件（表面安装部件）及其制造方法。 这种部件包括薄的导电层或层叠体，其设置有末端触点并且布置在电绝缘材料的支撑件上。 根据本发明，在平行于支撑件的表面的至少一个方向上的层或层的尺寸小于支撑件在所述方向上的尺寸，同时使支撑体的表面的一部分清除 层的层或层叠体的至少两侧以及层的层或层叠的端部触点位于不含该层或层叠层的支撑体的表面部分上，所述端部触点的厚度较大 比层或层叠层的厚度。 根据本发明的方法使得可以制造小尺寸电气部件，其中端部接触与部件的导电层或层叠层形成可靠的电连接。

公开(公告)号：WO1997030477A1

公开(公告)日：1997-08-21

申请号：PCT/US1997001873

申请日：1997-01-31

Applicant: OLIN CORPORATION

Inventor： OLIN CORPORATION ,  HOFFMAN, Paul, R.

IPC: H01L23/12

CPC classification number: H05K3/305 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H05K3/303 ,  H05K3/341 ,  H05K2201/0969 ,  H05K2201/10477 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2201/1084 ,  H05K2201/10969 ,  H05K2201/2036 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A surface mount package (10) to encapsulate one or more semiconductor devices (28) has a standoff (12) that maintains the thickness (D) of solder columns (26) bonding the package (10) to an external circuit (38). The standoff (12) either extends over or circumscribes a central portion (16) of the package base (14). To enhance the thermal performance of the standoff (12), a solderable layer (48) enhances soldering of the standoff (12) to the external circuit (38). In alternative embodiments, the standoff (12) contains a flange (58) having a plurality of apertures (62) useful for either mechanically locking an adhesive (34) or for enabling irradiation of an adhesive (34) by a light source. The standoff (12) may contain protrusions (64, 65) for alignment, strength or circuit (66) routing.

Abstract translation: 用于封装一个或多个半导体器件（28）的表面贴装封装（10）具有保持将封装（10）接合到外部电路（38）的焊料柱（26）的厚度（D）的间隔（12）。 间隔件（12）或者延伸到包装基部（14）的中心部分（16）上或外接。 为了增强支座（12）的热性能，可焊层（48）增强了支座（12）对外部电路（38）的焊接。 在替代实施例中，支座（12）包含具有多个孔（62）的凸缘（58），所述多个孔（62）可用于机械地锁定粘合剂（34）或用于通过光源照射粘合剂（34）。 间隙（12）可以包含用于对准，强度或电路（66）路由的突起（64,65）。

公开(公告)号：JP5591260B2

公开(公告)日：2014-09-17

申请号：JP2011543589

申请日：2009-12-17

Applicant: インテル・コーポレーション

Inventor： デーシュパンデー、アナンド ,  ナタラジャン、ベンカット ,  カバディ、アショク ,  キニ、ヴィッタル

IPC: H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K7/20

CPC classification number: H01L23/3677 ,  H01L23/40 ,  H01L23/427 ,  H01L2224/73253 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/325 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2201/10477 ,  H05K2201/10719

公开(公告)号：JP2011082221A

公开(公告)日：2011-04-21

申请号：JP2009230912

申请日：2009-10-02

Applicant: Fujitsu Ltd ,  富士通株式会社

Inventor： KOIDE MASATERU ,  MIZUTANI DAISUKE

IPC: H01L23/32 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K1/141 ,  H01L23/142 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/445 ,  H05K2201/10378 ,  H05K2201/10477 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To mount a semiconductor element package on a circuit board without increasing a cost and without degrading electric performances of the semiconductor element package and the circuit board.
SOLUTION: An interconnect board 20 interposed between a first circuit board 10 and a second circuit board 30 mounts the first circuit board 10 to the second circuit board 30. A metal plate 22 involved functions as a power supply layer or a ground layer electrically connected to a power supply terminal or a ground terminal of each of the first circuit board 10 and the second circuit board 30 through a first connection terminal 23-1 and a second connection terminal 23-2. A metal pile 24 electrically connects a signal terminal of the first circuit board 10 to the corresponding signal terminal of the second circuit board 30. The interconnect board 20 electrically connects the first circuit board 10 to the second circuit board 30, and an insulating layer 21 and the metal plate 22 function as a stiffener. Accordingly, stress caused due to deflection and warpage of the first circuit board 10 can be suppressed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：将半导体元件封装安装在电路板上，而不增加成本并且不降低半导体元件封装和电路板的电气性能。 插入在第一电路板10和第二电路板30之间的互连板20将第一电路板10安装到第二电路板30.金属板22用作电源层或接地层 通过第一连接端子23-1和第二连接端子23-2电连接到第一电路板10和第二电路板30中的每一个的电源端子或接地端子。 金属堆24将第一电路板10的信号端子与第二电路板30的对应的信号端子电连接。互连板20将第一电路板10电连接到第二电路板30，绝缘层21 并且金属板22用作加强件。 因此，可以抑制由于第一电路板10的偏转和翘曲引起的应力。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010171082A

公开(公告)日：2010-08-05

申请号：JP2009010274

申请日：2009-01-20

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： YAMAGUCHI SEIJI

IPC: H05K1/02

CPC classification number: H05K1/141 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/15153 ,  H05K1/183 ,  H05K3/281 ,  H05K3/284 ,  H05K2201/09072 ,  H05K2201/10477 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a circuit board preventing leakage and buildup of a sealing resin. SOLUTION: In a printed board 11 including a front surface 11A as a first surface and a rear surface 11B as a second surface opposed to the surface 11A, a hole 11C is formed through the printed board 11 so as to extend from the front surface 11A to the rear surface 11B, and a recessed part 15 is defined by holes respectively formed in a copper foil 12, a resist 13 and a Mylar sheet (R) 14 disposed on the back surface 11B side of the printed board 11. The hole 11C in the printed board 11 is exposed to the bottom of the recessed part 15. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种防止密封树脂渗漏和积聚的电路板。 解决方案：在包括作为第一表面的前表面11A和与表面11A相对的第二表面的后表面11B的印刷电路板11中，通过印刷电路板11形成孔11C，以便从 前表面11A到后表面11B，并且凹部15由分别形成在铜箔12，抗蚀剂13和布置在印刷电路板11的背面11B侧的聚酯薄片（R）14上的孔限定。 打印板11中的孔11C暴露于凹部15的底部。版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009147167A

公开(公告)日：2009-07-02

申请号：JP2007323764

申请日：2007-12-14

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： NAKAGAWA TOMOKATSU ,  HORIO MASAHIRO ,  MIYAZAKI TAKAHARU

IPC: H01L21/60

CPC classification number: H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/06154 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/049 ,  H05K2201/099 ,  H05K2201/10477

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device preventing disconnection of wiring.
SOLUTION: The device includes an interposer substrate mounted on a film substrate and a semiconductor element mounted on the interposer substrate. The interposer substrate includes a plurality of first substrate metal bumps, a plurality of first substrate pad metals 23 and a plurality of substrate wirings 24. The semiconductor element includes a plurality of element metal bumps bonded to the first substrate metal bumps by thermal clamping, a plurality of element pad metals 13 and a plurality of element wirings 14. The first substrate pad metals 23 and the element pad metals 13 have polygonal shapes where respective angles project outward. The substrate wirings 24 are connected to positions with spacing from vertexes of the angles of the corresponding first substrate pad metals 23. The element wirings 14 are connected to positions with spacing from the vertexes of the angles of the corresponding element pad metals 13.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种防止布线断开的半导体器件。 解决方案：该装置包括安装在薄膜基板上的插入器基板和安装在插入器基板上的半导体元件。 内插基板包括多个第一基板金属凸块，多个第一基板焊盘金​​属23和多个基板布线24.半导体元件包括通过热夹紧而与第一基板金属凸块接合的多个元件金属凸块， 多个元件焊盘金属13和多个元件布线14.第一基板焊盘金​​属23和元件焊盘金属13具有多个形状，其中各个角度向外突出。 衬底布线24连接到与对应的第一衬底焊盘金属23的角度的顶点间隔的位置。元件布线14连接到与对应的元件焊盘金属13的角度的顶点间隔的位置。

版权所有（C）2009，JPO＆INPIT