公开(公告)号：DE102007006853A1

公开(公告)日：2008-08-21

申请号：DE102007006853

申请日：2007-02-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIEFENBECK KLAUS ,  EISENER BERND ,  LANGGUTH GERNOT ,  MALEK KARLHEINZ ,  LEHRER CHRISTIAN ,  ALBERS SVEN ,  ROHRER EBERHARD

IPC: H01L23/60

Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.

公开(公告)号：DE102012108478A1

公开(公告)日：2013-03-21

申请号：DE102012108478

申请日：2012-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLAEYS DIETER ,  EISENER BERND ,  PFEIFER GUENTER ,  WILHELM DETLEF

IPC: H01L27/08 ,  H01L21/822 ,  H01L29/06 ,  H01L29/92

Abstract: Eine Ausführungsform könnte eine Halbleiterstruktur sein, aufweisend; ein Werkstück mit einer Vorderseite und einer Rückseite; und einen Kondensator, der in dem Werkstück angeordnet ist, wobei der Kondensator eine Bodenelektrode enthält, die elektrisch an eine Rückseite des Werkstücks gekoppelt ist. In einer Ausführungsform könnte die Bodenelektrode einen leitenden Pfad zur Vorderseite des Werkstücks bilden. In einer Ausführungsform könnte der Kondensator ein Grabenkondensator sein.

公开(公告)号：DE102005047000A1

公开(公告)日：2007-04-12

申请号：DE102005047000

申请日：2005-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERTHMANN HUBERT ,  EISENER BERND

IPC: H01L23/60 ,  H01L27/06 ,  H01L29/732

Abstract: A semiconductor structure for draining an overvoltage pulse comprises a first semiconductor region having a first doping type and a semiconductor layer arranged adjacent the first semiconductor region. The semiconductor layer includes an isolation structure configured to electrically isolate a second semiconductor region from a surrounding region. The second semiconductor region has a second doping type. A third semiconductor region having the first doping type is arranged adjacent the second semiconductor region and is disposed within an area limited by the isolation structure. A first contacting structure is configured to provide an electrical contact with the first semiconductor region, and a second contacting structure is configured to provide an electrical contact with the third semiconductor region. The first and second semiconductor regions are more highly doped than the second semiconductor region.

公开(公告)号：DE102006022360A1

公开(公告)日：2007-11-15

申请号：DE102006022360

申请日：2006-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKALSKI WINFRIED ,  ZANNOTH MARKUS ,  EISENER BERND ,  SEIDEL UWE

IPC: H01L23/58 ,  H01L21/76 ,  H05K9/00

公开(公告)号：DE10330838B4

公开(公告)日：2005-08-25

申请号：DE10330838

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AHRENS CARSTEN ,  POMPL STEFAN ,  BARTL ULF ,  WERTHMANN HUBERT ,  HARTUNG WOLFGANG ,  PEICHL RAIMUND ,  EISENER BERND ,  HERZUM CHRISTIAN

IPC: H01L21/329 ,  H01L29/417 ,  H01L29/872

Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.

公开(公告)号：DE10330838A1

公开(公告)日：2005-02-10

申请号：DE10330838

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AHRENS CARSTEN ,  POMPL STEFAN ,  BARTL ULF ,  WERTHMANN HUBERT ,  HARTUNG WOLFGANG ,  PEICHL RAIMUND ,  EISENER BERND ,  HERZUM CHRISTIAN

IPC: H01L21/329 ,  H01L29/417 ,  H01L29/872

Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.

公开(公告)号：DE102006022360B4

公开(公告)日：2009-07-09

申请号：DE102006022360

申请日：2006-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKALSKI WINFRIED ,  ZANNOTH MARKUS ,  EISENER BERND ,  SEIDEL UWE

IPC: H01L23/552 ,  H01L23/58 ,  H01L27/12 ,  H05K9/00

公开(公告)号：DE10311059A1

公开(公告)日：2004-10-07

申请号：DE10311059

申请日：2003-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AHRENS CARSTEN ,  EISENER BERND ,  HARTUNG WOLFGANG ,  HERZUM CHRISTIAN

IPC: H01L21/329 ,  H01L21/762 ,  H01L29/868 ,  H01Q1/38 ,  H01Q1/00

Abstract: Process for preparation of a semiconductor structure with troughs arranged in regions of different electrical conductivity comprises: substrate preparation, application of a first masking layer, etching of troughs, filling of these with an oxide layer, application and structuring of a second masking layer, removal of the oxide layer, removal of the second masking layer, and doping of the region surrounding the region not coated with the second masking layer. Independent claims are included for: (1) a semiconductor integrated circuit consisting of at least one PIN-diode (21) and a capacitor (23); (2) an antenna switch (20) consisting of at least one resistor (22), an inductance (24), a capacitor (23), and a PIN-diode; (3) a process for production of a PIN-diode.