公开(公告)号：US20020167828A1

公开(公告)日：2002-11-14

申请号：US10109555

申请日：2002-03-27

Applicant: Ballard Power Systems Corporation

Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC: H05K007/00

CPC classification number: H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H02M7/003 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K7/1432 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49009 ,  Y10T29/49117 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

公开(公告)号：US20020118560A1

公开(公告)日：2002-08-29

申请号：US09957568

申请日：2001-09-20

Inventor： Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett ,  Douglas Maly

IPC: H02M001/00

CPC classification number: H01L25/072 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/665 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A DC bus for use in a power module includes a positive DC conductor bus plate parallel with a negative DC conductor bus plate. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract translation: 用于功率模块的DC总线包括与负DC导体总线板平行的正直流导体母线板。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

公开(公告)号：US06198362B1

公开(公告)日：2001-03-06

申请号：US09264824

申请日：1999-03-09

Applicant: Takashi Harada ,  Hideki Sasaki

Inventor： Takashi Harada ,  Hideki Sasaki

IPC: H05K702

CPC classification number: H05K1/0234 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09354 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10446 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board is disclosed. A top layer power supply pattern and a top layer ground pattern are formed. The top layer power supply pattern and the top layer ground pattern are connected to a power supply layer and a ground layer through a plurality of viaholes, respectively. A plurality of capacitors or a plurality of capacitor resistor series circuits are disposed at predetermined intervals between the top layer power supply pattern and the top layer ground pattern.

Abstract translation: 公开了印刷电路板。 形成顶层电源图案和顶层接地图案。 顶层电源图案和顶层接地图案分别通过多个通孔连接到电源层和接地层。 多个电容器或多个电容器电阻器串联电路以顶层电源图案和顶层接地图案之间的预定间隔布置。

公开(公告)号：US06172305B2

公开(公告)日：2001-01-09

申请号：US09124346

申请日：1998-07-29

Applicant: Shigeo Tanahashi

Inventor： Shigeo Tanahashi

IPC: H04K103

CPC classification number: H05K1/0253 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0289 ,  H05K3/4644 ,  H05K2201/09345 ,  H05K2201/09672 ,  H01L2924/00

Abstract: First to fourth power wiring conductors and first to fourth ground wiring conductors are arranged on first to fourth insulating layers, respectively, and a first signal wiring conductor is arranged on the first or second insulating layer and a second signal wiring conductor is arranged on the third or fourth insulating layer. In a multilayer circuit board of the invention, the first to fourth insulating layers are sequentially overlaid in the following manner: each of wiring conductors on the same insulating layer is arranged substantially in parallel to each other, each set of the first power wiring conductor and the second ground wiring conductor, the first ground wiring conductor and the second power wiring conductor, the third power wiring conductor and the fourth ground wiring conductor, and the third ground wiring conductor and the fourth power wiring conductor is arranged so that two wiring conductors are opposed to each other nearly in parallel while interposing the insulating layer therebetween, and each wiring on the first and second insulating layers and each wiring on the third and fourth insulating layers intersect at a right angle, and wherein the first to fourth power wiring conductors and the first to fourth ground wiring conductors are connected via thorough conductors disposed through the insulating layers. The inventive multilayer circuit board ensures a uniform characteristic impedance on the signal wiring conductor to enable a stable power supply to a semiconductor device.

Abstract translation: 第一至第四电力布线导体和第一至第四接地布线导体分别布置在第一至第四绝缘层上，并且第一信号布线导体布置在第一或第二绝缘层上，第二信号布线导体布置在第三绝缘层上 或第四绝缘层。 在本发明的多层电路板中，第一至第四绝缘层依次叠加在同一绝缘层上的每个布线导体彼此平行地布置，每组第一电力布线导体和 第二接地布线导体，第一接地布线导体和第二布线导体，第三布线导体和第四布线导体以及第三布线导体和第四布线导体， 在绝缘层之间插入绝缘层时彼此相对并且在第一绝缘层和第二绝缘层上的每个布线和第三绝缘层和第四绝缘层上的每个布线相交成直角，并且其中第一至第四电力布线导体和 第一至第四接地布线导体经由穿过该布线的贯通导体连接 绝缘层。 本发明的多层电路板确保信号布线导体上的均匀的特征阻抗，以实现对半导体器件的稳定电源。

公开(公告)号：US20240107661A1

公开(公告)日：2024-03-28

申请号：US18472051

申请日：2023-09-21

Applicant: KYOCERA Document Solutions Inc.

Inventor： Shotaro Ikegami

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/10159 ,  H05K2201/10651

Abstract: A signal processing board includes a six-layer substrate. A plurality of signal transmission planes are formed in a first layer, a third layer, a fourth layer, and a sixth layer. A first ground plane is formed in a second layer. A first power supply plane is formed in a fifth layer and electrically connected to the first semiconductor element. A second power supply plane is formed in the fifth layer and electrically connected to the second semiconductor element. A second ground plane is formed in the fifth layer. A first bypass capacitor is electrically connected to the first power supply plane and the second ground plane. A second bypass capacitor is electrically connected to the second power supply plane and the second ground plane.

公开(公告)号：US20180153032A1

公开(公告)日：2018-05-31

申请号：US15574834

申请日：2015-05-29

Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

Inventor： Mitsumasa Sasaki

IPC: H05K1/02 ,  H05K1/18 ,  H05K5/00 ,  H02P25/16 ,  H02K11/33

CPC classification number: H05K1/0224 ,  H02K11/00 ,  H02K11/33 ,  H02P25/16 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0008 ,  H05K5/0026 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09354 ,  H05K2201/1009 ,  H05K2201/10166 ,  H05K2201/10287 ,  H05K2201/1034 ,  H05K2201/10522

Abstract: A semiconductor device of the present invention includes: a substrate (12) that is annular or partially annular; a first phase control circuit (14) provided on the substrate (12), the first phase control circuit being configured to control a first phase of a plurality of phases of a motor; a second phase control circuit (15) provided on the substrate (12) so as to be adjacent to the first phase control circuit (14) in a circumferential direction of the substrate (12), the second phase control circuit (15) being configured to control a second phase of the plurality of phases of the motor, the second phase being different from the first phase; a power supply wiring (18) disposed on one of an outer circumferential side and an inner circumferential side of the first phase control circuit (14) and the second phase control circuit (15) in a radial direction of the substrate (12), the power supply wiring (18) being connected to the first phase control circuit (14) and the second phase control circuit (15), and the power supply wiring (18) extending in the circumferential direction of the substrate (12); and a ground winding (19) disposed on an other one of the outer circumferential side and the inner circumferential side of the first phase control circuit (14) and the second phase control circuit (15) in the radial direction of the substrate (12), the ground winding (19) being connected to the first phase control circuit (14) and the second phase control circuit (15), and the ground winding (19) extending in the circumferential direction of the substrate (12).

公开(公告)号：US09839131B2

公开(公告)日：2017-12-05

申请号：US14918678

申请日：2015-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. Chamberlin ,  Andreas Huber ,  Harald Huels ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K1/02 ,  H05K3/40 ,  H05K1/09 ,  H05K1/16

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US20150255216A1

公开(公告)日：2015-09-10

申请号：US14201469

申请日：2014-03-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Shree Krishna Pandey ,  Irfan Khan ,  Nazanin Darbanian ,  John David Eaton

IPC: H01G4/30 ,  H05K1/18 ,  H01L49/02

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/242 ,  H01G4/35 ,  H05K1/0231 ,  H05K1/182 ,  H05K2201/09345 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.

Abstract translation: 具有低等效串联电感的电容器包括与连接在一起的交替的电极层并联布置的多个电极层，以形成电容器的两个电极。 第一组电极层通过外壁连接。 第二组电极层通过中心柱连接。 电容器上的端子可以在表面上间隔开，使得当电容器安装在印刷电路板或集成电路封装上时可以方便地布线信号。 端子可以包括在电容器的相对表面上以提供堆叠。 此外，其中一个端子基本上围绕另一个端子并且可以提供电磁屏蔽。

公开(公告)号：US08913401B2

公开(公告)日：2014-12-16

申请号：US13922349

申请日：2013-06-20

Applicant: Fuji Xerox Co., Ltd.

Inventor： Daisuke Iguchi

IPC: H05K1/11 ,  H05K7/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18

CPC classification number: H05K1/0243 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/162 ,  H05K1/181 ,  H05K2201/041 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A multilayer wiring board includes a signal electrode, a first power supply electrode, and a ground electrode, which are connected to a first element that outputs a signal, an electrode connected to a second element that receives the signal, a ground layer that serves as a return path for a return current of the signal, a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element, and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.

Abstract translation: 多层布线板包括信号电极，第一电源电极和接地电极，它们连接到输出信号的第一元件，连接到接收信号的第二元件的电极，用作 用于所述信号的返回电流的返回路径，与所述接地层相邻设置有电介质层并且向所述第一元件提供电力的第一电源层和与所述第一电源层独立地设置的第二电源层， 第一电源层并且向第二元件供电。 第一电源层使返回电流通过第一电源电极返回到第一元件，作为接地层和第一电源层之间的位移电流。

公开(公告)号：US08654539B2

公开(公告)日：2014-02-18

申请号：US13389364

申请日：2010-08-04

Applicant: Naoya Nakanishi

Inventor： Naoya Nakanishi

IPC: H05K1/18 ,  H01L21/02

CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10674

Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50.

Abstract translation: 本发明的目的是提供一种通过确保即使在通孔导体组中发生故障连接而产生电位的路径也可以提高连接可靠性的电容器配线布线基板。 在本发明的电容器配线基板中，电容器50容纳在芯体11中，并且在电容器50的上侧和下侧分别形成有第一和第二积累层12和13。