公开(公告)号：US20170290187A1

公开(公告)日：2017-10-05

申请号：US15507364

申请日：2015-09-17

Applicant: DENSO CORPORATION

Inventor： Takashi YOSHIMIZU ,  Yuuki SANADA

IPC: H05K7/14 ,  H01L23/31 ,  H01L23/053 ,  H05K1/18 ,  H05K1/02 ,  H01G2/06 ,  H01G2/10 ,  H05K1/11 ,  H01L23/367 ,  H01G2/08 ,  H01L23/498 ,  H01L23/10

CPC classification number: H05K7/1427 ,  H01G2/065 ,  H01G2/08 ,  H01G2/103 ,  H01L23/053 ,  H01L23/10 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49844 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/115 ,  H05K1/117 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10303 ,  H05K2201/10371 ,  H05K2201/1056 ,  H05K2201/1059 ,  H05K2203/1327 ,  H01L2924/00

Abstract: An electronic device includes a circuit board with an insulating substrate, a wiring at the substrate, an electronic component mounted at the substrate and electrically connected to the wiring, at least one through hole through the substrate from one surface to an opposite surface of the one surface of the substrate, and a conductive member arranged at a surface of the through hole and electrically connected to the wiring; and further includes: a sealing resin; and a cap including an annular connection with a part connected to the substrate and a recess recessed from the annular connection. Furthermore, in the cap, at least a part of the connection is connected to the substrate, the cap being sealed integrally with the electronic component by the sealing resin while arranging a space communicating with the through hole; and a terminal is inserted into the through hole and electrically connected to the wiring.

公开(公告)号：US09755391B2

公开(公告)日：2017-09-05

申请号：US14593735

申请日：2015-01-09

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Darko R. Popovic

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H01R43/20 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552

CPC classification number: H01R43/205 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.

公开(公告)号：US09627735B2

公开(公告)日：2017-04-18

申请号：US15159967

申请日：2016-05-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuki Wakabayashi ,  Bunta Okamoto ,  Satoshi Sasaki

IPC: H01P3/08 ,  H05K1/02 ,  H01P1/203 ,  H05K1/11

CPC classification number: H01P3/08 ,  H01P1/2039 ,  H01P3/082 ,  H05K1/0237 ,  H05K1/028 ,  H05K1/111 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: A high-frequency signal line includes a dielectric base with a first line portion and a second line portion each extending along a predetermined straight line parallel or substantially parallel to a predetermined direction, and a third line portion mutually connecting first side ends of the first line portion and the second line portion in the predetermined direction, a signal line, a first ground conductor located on the first side in the layer stacking direction of the signal line, a second ground conductor located on a second side in the layer stacking direction of the signal line, and one or more interlayer connection conductors connecting the first ground conductor and the second ground conductor. In the third line portion, the interlayer connection conductor is provided on the second side in the predetermined direction of the signal line when viewed from the layer stacking direction.

公开(公告)号：US20170094773A1

公开(公告)日：2017-03-30

申请号：US15215849

申请日：2016-07-21

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Il-Jong SEO ,  Ogura ICHIRO ,  Myung-Sam KANG ,  Tae-Hong MIN

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0206 ,  H05K1/0207 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/049 ,  H05K2201/06 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/09645 ,  H05K2201/10674

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board may include a core layer, a metal layer disposed on the core layer, and a heat dissipation unit disposed to pass through the core layer in across a thickness of the core layer.

公开(公告)号：US20170093456A1

公开(公告)日：2017-03-30

申请号：US15276179

申请日：2016-09-26

Applicant: Electrochem Solutions, Inc.

Inventor： Gregory G. Decker ,  Brian R. Peterson ,  Eric Jankins

IPC: H04B1/40 ,  H05K1/11 ,  H05K1/02 ,  H02J50/10 ,  H02M7/155

CPC classification number: H04B1/40 ,  H02J7/0029 ,  H02J7/025 ,  H02J50/10 ,  H02J50/12 ,  H02J50/80 ,  H02J2007/0037 ,  H02J2007/004 ,  H02M7/155 ,  H04B5/0031 ,  H04B5/0037 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/0707 ,  H05K2201/09609

Abstract: A system for harnessing and conditioning wirelessly transmitted electrical energy by near field magnetic induction configured with various magnetic field shielding embodiments is disclosed. The shielding embodiments are designed to minimize electromagnetic interference and induced electrical current. The system comprises an electrical energy capture circuit and an RF communication circuit. The electrical energy capture circuit conditions and modifies the wirelessly received electrical energy. The RF communication circuit enables the system to wirelessly communicate with its sub-circuits and other energy capture systems. The system comprises a tunable band stop filter that is electrically connected to the RF communication sub-circuit. In addition, the RF communication sub-circuit is configured with opposing electrically conductive plates that isolate and shield the circuit from an oscillating magnetic field.

公开(公告)号：US09277657B2

公开(公告)日：2016-03-01

申请号：US14222077

申请日：2014-03-21

Applicant: KYOCERA SLC Technologies Corporation

Inventor： Hiroyuki Fukushima ,  Fumio Kumokawa

IPC: H05K1/11 ,  H05K7/00 ,  H05K3/46 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K3/4602 ,  H01L24/81 ,  H05K1/0271 ,  H05K3/3436 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09781

Abstract: A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.

Abstract translation: 布线基板包括具有多个通孔的芯基板，以及在芯基板的上表面和下表面上交替层叠的积层绝缘层和积层布线层，其中第一通孔组布置在第一区域中 所述芯板处于第一配置密度，所述第一区域与所述半导体元件连接焊盘形成区域相对，第二通孔组以比所述第一布置密度低的第二布置密度布置在第二区域中，所述第二区域 位于所述芯基板的外周部分并且远离所述第一区域，并且第三通孔组以比所述第二布置密度高的第三布置密度设置在第三区域中，所述第三区域位于所述第二区域之间， 第一区和第二区。

公开(公告)号：US20150257256A1

公开(公告)日：2015-09-10

申请号：US14633342

申请日：2015-02-27

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Takashi Sato ,  Ruofan Tang

IPC: H05K1/02 ,  H01L23/544 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K1/0269 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/115 ,  H05K3/4682 ,  H05K2201/09409 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/09936 ,  H01L2924/00

Abstract: A wiring substrate includes wiring layers and insulation layers alternately stacked. Via holes are formed in the insulation layers. First via wirings are formed in the via holes to electrically connect the wiring layers to one another. Through holes extend through a lowermost one of the insulation layers in a thickness direction. The lowermost insulation layer covers a lowermost one of the wiring layers. Second via wirings are formed in the through holes to define an identification mark that is identifiable as a specific shape including a character, a symbol, or a combination thereof. A lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and is flush with a lower surface of the lowermost wiring layer.

Abstract translation: 布线基板包括交替堆叠的布线层和绝缘层。 在绝缘层中形成通孔。 首先通过布线形成通孔，以将布线层彼此电连接。 通孔在厚度方向上延伸穿过绝缘层中的最下面一个。 最下面的绝缘层覆盖最下面的一个布线层。 第二通孔布线形成在通孔中以形成可识别为包括字符，符号或其组合的特定形状的识别标记。 每个第二通孔布线的下表面从最下层绝缘层的下表面露出，并且与最下布线层的下表面齐平。

公开(公告)号：US20140367854A1

公开(公告)日：2014-12-18

申请号：US13927470

申请日：2013-06-26

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/00

CPC classification number: H01L23/49833 ,  H01L23/3142 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4046 ,  H05K3/4688 ,  H05K2201/0218 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/041 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012

Abstract: Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate.

Abstract translation: 为模制IC封装的互连结构提供了各种实例。 在一个示例中，其中，IC封装包括基板和插入件。 多个导电元件在基板的表面和插入件的表面之间提供物理和电接触。 设置在基板和插入件的表面之间的间隔元件在基板和插入件的表面之间提供最小的间隔。 在一些实施方案中，支架元件设置在设置在基板的表面上的IC管芯和插入件的表面之间。 在另一示例中，一种方法包括将导电元件耦合到插入件的表面，附接支架元件，将导电元件耦合到基板的表面，以及在插入器和基板之间形成嵌入层。 支座元件限定了插入件和基板之间的最小间隙。

公开(公告)号：US20140355213A1

公开(公告)日：2014-12-04

申请号：US14289126

申请日：2014-05-28

Applicant: Davide BETTONI ,  Giorgio STIRANO

Inventor： Davide BETTONI ,  Giorgio STIRANO

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0204 ,  H05K1/0206 ,  H05K1/0265 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/181 ,  H05K3/0061 ,  H05K3/42 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10053 ,  H05K2201/10166

Abstract: An electronic device may include at least one power component and a printed circuit board. The at least one power component may include a main body and a lead. The printed circuit board may include at least two conductive layers parallel to a plane. The printed circuit board may further include a mounting element and a conductor. The mounting element may include first conductive tubes. The conductor may include second conductive tubes. The first conductive tubes and the second conductive tubes may elongate through a thickness of the printed circuit board along a direction substantially perpendicular to the plane. The main body of the at least one power component may be fixed to the mounting element. The lead of the at least one power component may be fixed to the conductor.

Abstract translation: 电子设备可以包括至少一个功率部件和印刷电路板。 所述至少一个功率部件可以包括主体和引线。 印刷电路板可以包括平行于平面的至少两个导电层。 印刷电路板还可以包括安装元件和导体。 安装元件可以包括第一导电管。 导体可以包括第二导电管。 第一导电管和第二导电管可以沿着基本上垂直于该平面的方向延伸穿过印刷电路板的厚度。 至少一个功率部件的主体可以固定到安装元件。 至少一个功率部件的引线可以固定到导体。

公开(公告)号：US20140111951A1

公开(公告)日：2014-04-24

申请号：US13654450

申请日：2012-10-18

Applicant: INFINEON TECHNOLOGIES AUSTRIA AG

Inventor： Martin STANDING ,  Andrew ROBERTS

IPC: H05K1/18 ,  H05K3/20 ,  H05K1/11

CPC classification number: H05K1/0207 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K1/186 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/10166 ,  H05K2201/10416 ,  H05K2201/10492 ,  H05K2201/10515 ,  Y10T29/49128 ,  H01L2924/00

Abstract: Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB.

Abstract translation: 器件和技术的代表性实现提供了诸如设置在多层印刷电路板（PCB）的不同层上的部件（例如芯片）的改进的电性能。 在一个示例中，组件可以嵌入在PCB的层内。 位于两个组件层或层组之间的绝缘层包括可以被策略地定位以提供部件之间的电连接的导电部分。 导电部分也可以布置成改善PCB的点之间的热导率。