公开(公告)号：US20040159921A1

公开(公告)日：2004-08-19

申请号：US10775736

申请日：2004-02-10

Inventor： Stephen Moxham ,  William Stephenson

IPC: H01L021/44 ,  H01L023/495

CPC classification number: H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to receive a flowable conductive material, and can further have at least two first elongated members connected and extending outwardly from the first bond site. Each first elongated member can be configured to receive at least a portion of the flowable conductive material from the first bond site, with none of the first elongated members being electrically coupled to the microelectronic substrate. The assembly can further include a second connection structure that is electrically coupled to the microelectronic substrate and that can include second elongated members extending away from a second bond site. The number of second elongated members can be equal to the number of first elongated members.

Abstract translation: 一种用于支撑微电子衬底的方法和装置。 该装置可以包括微电子衬底和承载微电子衬底的支撑构件。 该装置还可以包括由支撑构件承载的第一连接结构。 第一连接结构可以具有构造成接收可流动的导电材料的第一接合位置，并且还可以具有连接并从第一接合位置向外延伸的至少两个第一细长构件。 每个第一细长构件可以被构造成从第一接合位置接收可流动的导电材料的至少一部分，而第一细长构件没有一个电耦合到微电子衬底。 组件还可以包括电耦合到微电子衬底的第二连接结构，并且可以包括远离第二接合位置延伸的第二细长构件。 第二细长构件的数量可以等于第一细长构件的数量。

公开(公告)号：US20040159460A1

公开(公告)日：2004-08-19

申请号：US10481252

申请日：2004-02-05

Inventor： George Passiopoulos ,  Ilpo Kokkonen ,  Olli Salmela

IPC: H01B007/08

CPC classification number: H05K1/0237 ,  H01P3/006 ,  H01P3/02 ,  H01P3/023 ,  H01P3/081 ,  H01P3/085 ,  H05K1/0224 ,  H05K1/0263 ,  H05K2201/09672 ,  H05K2201/0979

Abstract: A conductive structure having a conductor for carrying a signal at a one or more operating frequencies of the structure, the conductor comprising: at least two electrically conductive strips spaced apart by a dielectric and arranged in parallel to extend from a first node to a second node, the conductive strips being interconnected between the nodes by at least one inter-strip electrically conductive connection through the dielectric; the maximum physical dimension of the or each inter-strip connection and the maximum physical separation of potentially successive inter-strip connections being equal to or less than one quarter of the free space wavelength corresponding to the minimum operating frequency of the structure.

Abstract translation: 一种导电结构，具有用于在该结构的一个或多个工作频率处传送信号的导体，所述导体包括：至少两个由电介质隔开并且平行布置的导电条，以从第一节点延伸到第二节点 ，所述导电条通过所述电介质至少一个带间导电连接在所述节点之间互连; 每个条带间连接的最大物理尺寸和潜在连续条带间连接的最大物理间隔等于或小于对应于结构的最小工作频率的自由空间波长的四分之一。

公开(公告)号：US20040154827A1

公开(公告)日：2004-08-12

申请号：US10360575

申请日：2003-02-06

Applicant: R-Tec Corporation

Inventor： Scott Patrick Terrell ,  Clifton Jay Seusy ,  Robert Calhoun Cannon ,  Darrell Kent Mason ,  Brandon Chad Bailey ,  Douglas G. Hastings

IPC: H01R004/58 ,  H01K003/10

CPC classification number: H01R13/2414 ,  H05K1/113 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/247 ,  H05K3/325 ,  H05K3/326 ,  H05K3/427 ,  H05K2201/0314 ,  H05K2201/035 ,  H05K2201/0969 ,  H05K2201/0979 ,  H05K2201/10378 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: An interposer with a contact well, a layer that isolates one side of the interposer from the other side, for isolations of off gasses, and an optional elastomeric pad and a hard stop layer. Included is a method of making the interposer.

Abstract translation: 具有接触阱的插入器，将隔离物的一侧与另一侧隔离的层，用于隔离气体，以及可选的弹性垫和硬停止层。 包括一种制作插值器的方法。

公开(公告)号：US20040147165A1

公开(公告)日：2004-07-29

申请号：US10716808

申请日：2003-11-19

Inventor： Brian Celella ,  Vito Pagliarulo ,  Daniel Mullin

IPC: H01R024/00

CPC classification number: H05K1/0248 ,  H05K1/0228 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10189

Abstract: A printed circuit board providing crosstalk compensation. The printed circuit board includes first plated through holes for receiving a first connecting component and second plated through holes for receiving a second connecting component. A signal carrying trace transmits a signal from one of the first plated through holes to one of the second plated through holes. A phase delay control trace is in electrical connection with the one of the first plated through holes. The phase delay control trace affects phase delay of the signal from the one of the first plated through holes to the one of the second plated through holes.

Abstract translation: 提供串扰补偿的印刷电路板。 印刷电路板包括用于接收第一连接部件的第一电镀通孔和用于接收第二连接部件的第二电镀通孔。 信号承载轨迹将信号从第一电镀通孔中的一个传递到第二电镀通孔中的一个。 相位延迟控制迹线与第一电镀通孔中的一个电连接。 相位延迟控制迹线影响信号从第一电镀通孔中的一个到第二电镀通孔中的一个的相位延迟。

公开(公告)号：US06720652B2

公开(公告)日：2004-04-13

申请号：US10213185

申请日：2002-08-05

Applicant: Salman Akram ,  James M. Wark ,  David R. Hembree

Inventor： Salman Akram ,  James M. Wark ,  David R. Hembree

IPC: H01L2334

CPC classification number: H01L23/5382 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/14 ,  H05K1/0292 ,  H05K1/0295 ,  H05K2201/0979 ,  H05K2201/10159 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method and apparatus for repair of a multi-chip module, such as a memory module, is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract translation: 提供了一种用于修复诸如存储器模块的多芯片模块的方法和装置，其中在多芯片模块的基板上提供至少一个冗余或辅助芯片连接位置。 辅助芯片安装位置优选地提供用于连接多于一种类型的替换半导体芯片的触点。 因此，当发现多芯片模块上的一个或多个芯片完全或部分缺陷时，可以选择至少一个替换芯片并附加到辅助位置，以提供额外的存储器以使模块回到其设计能力。

公开(公告)号：US06711640B1

公开(公告)日：2004-03-23

申请号：US09823147

申请日：2001-03-29

Applicant: Michael W. Leddige ,  James A. McCall

Inventor： Michael W. Leddige ,  James A. McCall

IPC: G06F1300

CPC classification number: H05K1/0248 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/0979 ,  H05K2201/10159

Abstract: A computer motherboard is described. That motherboard includes a memory controller and a memory section. A first trace couples the memory controller to the memory section, and a second trace couples the memory controller to the memory section. The first trace is joined with the second trace at the memory controller, the second trace is routed in parallel with the first trace, and the second trace is longer than the first trace. Also described is a computer system that includes this motherboard and a memory card.

Abstract translation: 描述了计算机主板。 该主板包括一个内存控制器和一个内存部分。 第一迹线将存储器控制器耦合到存储器部分，并且第二迹线将存储器控制器耦合到存储器部分。 第一个跟踪与存储器控制器上的第二个跟踪相连，第二个跟踪与第一个跟踪并行，第二个跟踪长于第一个跟踪。 还描述了包括该主板和存储卡的计算机系统。

公开(公告)号：US06675313B2

公开(公告)日：2004-01-06

申请号：US10329494

申请日：2002-12-27

Applicant: David Cuthbert

Inventor： David Cuthbert

IPC: G06F104

CPC classification number: H05K1/0248 ,  G06F1/10 ,  H05K1/0293 ,  H05K3/027 ,  H05K2201/09263 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1115 ,  H05K2203/1338 ,  H05K2203/171 ,  H05K2203/175

Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

Abstract translation: 描述了一种用于减少包括互连第一节点和第二节点的多个导电迹线的印刷电路板上的定时偏移的装置和方法。 至少一个部分从至少一个印刷电路板迹线移除，从而切断迹线并防止从第一节点传递到第二节点的信号不跟随切断的迹线。 以这种方式，可以调整信号路径长度以减少电路中的定时偏差。 通过使用激光，CVD，路由器，等离子体或者通过使足够的电流通过弱化区域从迹线中去除部分。

公开(公告)号：US20030213767A1

公开(公告)日：2003-11-20

申请号：US10426326

申请日：2003-04-29

Inventor： Robert Edward Belke JR. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty JR.

IPC: H01B013/00

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/0979 ,  H05K2201/09854 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.

Abstract translation: 具有选择性地形成的具有改善的焊料润湿特性的孔或腔26的多层电子电路板设计10。

公开(公告)号：US20030134528A1

公开(公告)日：2003-07-17

申请号：US10341468

申请日：2003-01-14

Applicant: YAZAKI CORPORATION

Inventor： Yoshiyuki Tanaka ,  Hiroyuki Ashiya ,  Yayoi Maki

IPC: H01R012/00

CPC classification number: B60R16/0238 ,  H01R9/2466 ,  H05K3/301 ,  H05K3/306 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/0979 ,  H05K2201/10424 ,  H05K2201/10651 ,  H05K2201/10757 ,  H05K2201/10856 ,  H05K2201/2036 ,  Y10S439/949

Abstract: The terminal mounting structure includes a board (21). The structure includes a terminal (26) mounted on the board. The terminal includes a first end (26a) removably connected to a connection component (16, 17, 18). The terminal includes a second end (26b) soldered to the board in a raised position. The terminal includes a bent portion (26d) at intermediate of the terminal and at respective angles relative to respective first and second ends. The structure includes a retaining member (30, 40) facing the board with a space therebetween, and retaining the bent portion.

Abstract translation: 端子安装结构包括板（21）。 该结构包括安装在板上的端子（26）。 端子包括可移除地连接到连接部件（16,17,18）的第一端（26a）。 端子包括在升高位置焊接到板的第二端（26b）。 端子包括在端子的中间并且相对于相应的第一和第二端成各个角度的弯曲部分（26d）。 该结构包括面对板的保持构件（30,40），并且保持弯曲部分。

公开(公告)号：US06552635B1

公开(公告)日：2003-04-22

申请号：US09548578

申请日：2000-04-13

Applicant: James R. Sherman ,  Ray B. Jones ,  Barry B. Pruett

Inventor： James R. Sherman ,  Ray B. Jones ,  Barry B. Pruett

IPC: H01P308

CPC classification number: H01P3/087 ,  H05K1/024 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/0979 ,  H05K2201/2036

Abstract: A suspended transmission line includes a dielectric support layer having a first side and a second side. The conductor is supported between first and second ground planes and includes a first part supported on the first side of the support layer and a second part supported on the second side of the support layer. A third part of the conductor connects the first and second parts at spaced intervals along the conductor. A propagation structure is disposed between the ground planes and operable to substantially contain an electric field generated by a signal transmitted on the conductor.

Abstract translation: 悬挂的传输线包括具有第一侧和第二侧的电介质支撑层。 导体被支撑在第一和第二接地平面之间，并且包括支撑在支撑层的第一侧上的第一部分和支撑在支撑层的第二侧上的第二部分。 导体的第三部分沿着导体以间隔的间隔连接第一和第二部分。 传播结构设置在接地层之间并且可操作以基本上包含由在导体上传输的信号产生的电场。