公开(公告)号：US5890282A

公开(公告)日：1999-04-06

申请号：US695487

申请日：1996-08-12

Applicant: Denis J. Leveque ,  James R. Jaeschke

Inventor： Denis J. Leveque ,  James R. Jaeschke

IPC: H01H1/58 ,  H05K3/20 ,  H05K3/28 ,  H05K3/30 ,  H05K3/38

CPC classification number: H05K3/301 ,  H01H1/58 ,  H05K3/202 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K3/281 ,  H05K3/386 ,  Y10T29/4913

Abstract: A control and panel assembly using a thin dielectric carrier strip upon which a sheet of conductive material is adhesively attached. The conductive sheet is perforated to form an array of spaced parallel discrete conductors. The conductors are initially formed as interconnected by transverse webs which are frangibly removed after attachment to the carrier. Individual stand up connectors are then attached to each of the conductors to form a carrier sub-assembly and the terminals are inserted through slots in a dielectric deck plate. Individual user actuated control components are then plugged directly into the terminals with user actuated shafts or levers extending through deck plate and carrier strip.

Abstract translation: 一种使用薄介电载体条的控制和面板组件，导电材料片粘附在该绝缘载体带上。 导电片被穿孔以形成间隔开的平行离散导体的阵列。 导体最初形成为通过横向腹板互连，在连接到载体上之后，导体被易碎地移除。 然后将单独的立起连接器连接到每个导体以形成载体子组件，并且端子通过介电甲板板中的槽插入。 然后，用户致动的控制组件直接插入终端，用户驱动的轴或杠杆延伸穿过甲板板和载体带。

公开(公告)号：US5884398A

公开(公告)日：1999-03-23

申请号：US839760

申请日：1997-04-15

Applicant: Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

Inventor： Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

IPC: B23K20/00 ,  C23C18/16 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/603 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H05K1/14 ,  H05K3/20 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H01R9/00

CPC classification number: B23K20/004 ,  B23K20/007 ,  C25D7/12 ,  G01R31/2884 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H05K3/326 ,  H05K3/4015 ,  B23K2201/40 ,  C25D21/02 ,  C25D5/08 ,  C25D5/22 ,  G01R31/2886 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K3/20 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4092 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.

Abstract translation: 弹性接触结构直接安装在半导体晶片上的接合焊盘上，在裸片与半导体晶片分离（分离）之前。 这使得半导体管芯能够通过具有设置在其表面上的多个端子的电路板等连接到半导体管芯来进行（例如，测试和/或烧入）。 接下来，半导体管芯可以从半导体晶片分离，因此可以使用相同的弹性接触结构来实现半导体管芯和其他电子部件（例如布线基板，半导体封装等）之间的互连。 使用本发明的全金属复合互连元件作为弹性接触结构，可以在至少150℃的温度下进行老化，并且可以在少于60分钟内完成。

公开(公告)号：US5850693A

公开(公告)日：1998-12-22

申请号：US631701

申请日：1996-04-10

Applicant: Orest D. Guran ,  Donald E. Wood ,  Richard J. Middlehurst

Inventor： Orest D. Guran ,  Donald E. Wood ,  Richard J. Middlehurst

IPC: H01R12/51 ,  H01R43/02 ,  H01R43/20 ,  H05K1/14 ,  H05K3/30 ,  H01R43/00

CPC classification number: H01R43/205 ,  H05K3/303 ,  H01R12/57 ,  H01R43/0256 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10946 ,  Y02P70/613 ,  Y10T29/49153 ,  Y10T29/49222

Abstract: An electronic socket adapter includes an insulative carrier and an array of a plurality of surface mount contacts carried on the base. The pins may be floatably mounted on the carrier. A plurality of relatively large openings are formed in the carrier between adjacent contacts in the array. The openings provide improved heat flow in the region of the surface mount portions of the contacts and also provide for visualization of the surface mount portions of the contacts during and after soldering.

Abstract translation: 电子插座适配器包括绝缘载体和承载在基座上的多个表面安装触头的阵列。 销可以可浮动地安装在托架上。 在阵列中的相邻触点之间的载体中形成多个相对较大的开口。 这些开口在接触件的表面安装部分的区域中提供改善的热流，并且还提供在焊接期间和之后对触点的表面安装部分的可视化。

公开(公告)号：US5625944A

公开(公告)日：1997-05-06

申请号：US480650

申请日：1995-06-07

Applicant: William E. Werther

Inventor： William E. Werther

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K7/10 ,  H01K3/10

CPC classification number: H05K1/141 ,  H05K3/3415 ,  H05K7/1084 ,  H05K7/1092 ,  H05K1/0262 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/368 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.

Abstract translation: 公开了用于互连集成电路，特别是预先包装的集成电路的组件和方法。 由引脚载体，一组焊盘（例如用于接收表面安装的集成电路）和耦合焊盘和引脚的一组导电路径组成的多电平电气组件可以将一个或多个集成电路连接到 插座或电路板的其他连接区域。 路径通过多层互连板，其可以被配置为允许将焊盘任意平移到引脚用于不同目的，或者允许附加电路元件（例如协处理器或无源电路）与路径的耦合。 还公开了用于形成组件的本发明的方法以及组件的实施例可用于增加电路板密度的本发明的系统。

公开(公告)号：US5607313A

公开(公告)日：1997-03-04

申请号：US394831

申请日：1995-02-27

Applicant: Bengt E. Nyman

Inventor： Bengt E. Nyman

IPC: H01R12/57 ,  H05K3/34 ,  H05K3/40 ,  H01R9/09

CPC classification number: H01R12/57 ,  H05K3/3421 ,  H05K3/4015 ,  H05K2201/10318 ,  H05K2201/1059 ,  H05K2201/10916 ,  H05K2201/10962 ,  Y02P70/613

Abstract: A method and device for improved assembly to hole-free PCBs of high aspect ratio components or any other components that are not easily assembled to a hole-free PCB by standard surface-mount technology (SMT), such as pins, lugs, tabs, and test points. A metal or other electrically conductive member having one or more holes ("holed component") is mounted to the PCB, typically on a solder pad on the PCB. The said electrically conductive member, will have a low aspect ratio. The hole, which may be round, rectangular, or threaded, is sized to provide an interference fit with the male projection of the component which will be inserted within the hole. The holed component, like other low aspect ratio SMT components, may be delivered on tape and reel and conventional surface mount or pick and place equipment is used to surface mount the holed component on the hole-free PCB, following which the holed component is soldered in place. Then, the male projections of the components can be press-fitted into the holes of one or more of such soldered holed components in the same manner as such components were previously interference fitted into the holes of PCBs, using high speed inserter machines.

Abstract translation: 一种方法和装置，用于通过标准表面贴装技术（SMT）例如针，凸耳，凸片等将高纵横比部件或其他不能轻易组装到无孔PCB的组件的无孔PCB组装改进， 和测试点。 具有一个或多个孔（“孔组件”）的金属或其它导电构件通常安装在PCB上，PCB上的焊盘上。 所述导电构件将具有低纵横比。 该孔可以是圆形的，矩形的或螺纹的，其尺寸被设计成提供与插入孔内的部件的阳突出物的过盈配合。 与其他低纵横比的SMT组件一样，孔组件可以在磁带和卷轴上传送，并且常规的表面贴装或拾取和放置设备用于将无孔PCB上的孔组件表面安装，然后将孔组件焊接 到位。 然后，使用高速插入机，将这些部件的凸形突起可以按照相同的方式压配合到一个或多个这样的焊接孔部件的孔中，这些部件预先被干涉地装配到PCB的孔中。

公开(公告)号：US5067007A

公开(公告)日：1991-11-19

申请号：US645357

申请日：1991-01-24

Applicant: Kanji Otsuka ,  Masao Kato ,  Takashi Kumagai ,  Mitsuo Usami ,  Shigeo Kuroda ,  Kunizo Sahara ,  Takeo Yamada ,  Seiji Miyamoto ,  Yuuji Shirai ,  Takayuki Okinaga ,  Kazutoshi Kubo ,  Hiroshi Tachi ,  Masayuki Kawashima

Inventor： Kanji Otsuka ,  Masao Kato ,  Takashi Kumagai ,  Mitsuo Usami ,  Shigeo Kuroda ,  Kunizo Sahara ,  Takeo Yamada ,  Seiji Miyamoto ,  Yuuji Shirai ,  Takayuki Okinaga ,  Kazutoshi Kubo ,  Hiroshi Tachi ,  Masayuki Kawashima

IPC: H01L23/50 ,  H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L23/49555 ,  H01L23/433 ,  H01L23/49579 ,  H01L23/49811 ,  H05K3/3426 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K2201/0308 ,  H05K2201/10318 ,  H05K2201/10681 ,  H05K2201/10704 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Abstract translation: 随着制造高密度和小尺寸集成电路的趋势，已经尝试增加封装引脚的数量。 本发明提供了提高具有增加的引脚数的表面安装型封装的可靠性的技术。 也就是说，当封装被安装在布线基板上时，从轴向接收负载的引线销显示出小于接合部处的焊料的接合强度的弯曲强度。 为了实现该目的，引脚由具有大弹性的材料制成，例如纤维增强材料，变形假弹性材料，超高张力材料或耐热超高张力材料。

公开(公告)号：US3375323A

公开(公告)日：1968-03-26

申请号：US53869666

申请日：1966-03-30

Applicant: MARCONI CO LTD

Inventor： JAMES MAYHEW ANTONY

IPC: H01R12/00 ,  H05K1/00 ,  H05K1/11 ,  H05K3/32 ,  H05K3/42

CPC classification number: H01R12/523 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/328 ,  H05K2201/09472 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10893

公开(公告)号：US10135159B1

公开(公告)日：2018-11-20

申请号：US15601362

申请日：2017-05-22

Applicant: Rosemount Aerospace Inc.

Inventor： Tim DeAngelo

IPC: H01R12/58 ,  H05K3/46 ,  H05K3/36 ,  H01R43/20 ,  H01R3/00 ,  H05K1/14 ,  H05K3/00

CPC classification number: H01R12/58 ,  H01R12/52 ,  H01R43/205 ,  H05K1/11 ,  H05K1/144 ,  H05K1/145 ,  H05K3/007 ,  H05K3/366 ,  H05K3/368 ,  H05K3/4644 ,  H05K2201/042 ,  H05K2201/10189 ,  H05K2201/10318 ,  H05K2201/10325

Abstract: A circuit card assembly includes a first printed wiring board with a first receiving feature and a trace attached to the first printed wiring board. The three dimensional trace is formed by layer-by-layer additive manufacturing. The three dimensional trace includes first and second ends. The first end of the three dimensional trace engages with the first receiving feature of the first printed wiring board. The second end of the three dimensional trace is configured to engage with a second printed wiring board.

公开(公告)号：US10057989B1

公开(公告)日：2018-08-21

申请号：US15483417

申请日：2017-04-10

Applicant: TactoTek Oy

Inventor： Mikko Heikkinen ,  Antti Keränen ,  Jarmo Sääski ,  Ronald H. Haag

IPC: H05K1/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/28

CPC classification number: H05K1/185 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/112 ,  H05K1/142 ,  H05K1/148 ,  H05K1/184 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/284 ,  H05K3/368 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09063 ,  H05K2201/09754 ,  H05K2201/10189 ,  H05K2201/10265 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: Multilayer structure, including a substrate film having a first and second opposite side, said substrate film including electrically insulating material, conductive traces on the first side of the substrate film for establishing a predetermined circuit design, a connector element laid upon the first side of, said substrate film, one side of the connector element facing the structure internals and the other, opposite side facing the environment on the second side of the substrate film including a number of electrically conductive contact members electrically connected to the circuit on the first side of the substrate film and configured to contact one or more electrical contact members of an external element responsive to mating the external element with the connector element, and a plastic layer molded onto the substrate film and the connector element so as to cover said one side of the connector element and the circuit.

公开(公告)号：US09949398B2

公开(公告)日：2018-04-17

申请号：US15363429

申请日：2016-11-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Guodong Zhang ,  Jian Zhang ,  Jianping Shu

IPC: H01R13/648 ,  H05K7/14 ,  H01R12/75 ,  H05K1/18 ,  H01R12/70 ,  H01R12/79 ,  H05K1/14 ,  H04Q1/02

CPC classification number: H05K7/1439 ,  H01R12/7005 ,  H01R12/75 ,  H01R12/79 ,  H04Q1/15 ,  H05K1/141 ,  H05K1/18 ,  H05K7/1449 ,  H05K7/1451 ,  H05K7/1452 ,  H05K2201/044 ,  H05K2201/10318 ,  H05K2201/10356

Abstract: A backplane and a communications device are disclosed. The backplane includes: at least one fixing plate, multiple connectors, and multiple flexible cables, where signal connection is implemented between corresponding connectors by means of the flexible cables, each of the connectors is provided with a housing and multiple signal pins installed on the housing, and the housing is installed on the fixing plate and is provided with a jack for insertion of a connector of a subcard in the communications device; one end of each signal pin is inserted into the jack, and the other end is connected to each flexible cable. When the communications device provided with the backplane transmits a high-rate signal, transmission quality and a transmission rate are relatively high.