公开(公告)号：US20150382480A1

公开(公告)日：2015-12-31

申请号：US14750186

申请日：2015-06-25

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Guy Frick ,  Thomas J. Colosimo, JR. ,  Horst Clauberg

IPC: H05K3/34 ,  B23K3/08 ,  B23K3/04 ,  B23K1/00 ,  B23K1/20

CPC classification number: H05K3/34 ,  B23K1/0016 ,  B23K1/203 ,  B23K3/04 ,  B23K3/082 ,  B23K2101/42 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/75161 ,  H01L2224/75184 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81204 ,  H05K3/3489 ,  H05K3/3494 ,  H05K2201/10674 ,  H05K2203/04 ,  H01L2924/014

Abstract: A thermocompression bonder is provided. The thermocompression bonder includes: a bond head including a heated bonding tool for bonding a semiconductor element to a substrate; and a flux application tool for applying a flux material to conductive contacts of the substrate prior to bonding of the semiconductor element to the substrate.

Abstract translation: 提供热压接机。 热压接机包括：接合头，其包括用于将半导体元件接合到衬底的加热焊接工具; 以及焊剂施加工具，用于在将半导体元件接合到衬底之前将焊剂材料施加到衬底的导电触点。

公开(公告)号：US20150380391A1

公开(公告)日：2015-12-31

申请号：US14848504

申请日：2015-09-09

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Yong HA WOO ,  E-Tung CHOU ,  Wen-Lun LO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H05K1/09 ,  H05K1/11

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/09 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0379 ,  H05K2201/09836 ,  H05K2201/10674 ,  H05K2203/0384 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided.

Abstract translation: 封装基板包括电路板，多个第一导电柱和多个第二导电柱。 电路板包括形成在第一基底的第一表面上的第一基底和第一导电图案层。 第一导电柱从第一导电图案层延伸并电连接到第一导电图案层。 第二导电柱从第一导电图案层延伸并与之电连接。 每个第二导电柱的高度大于每个第一导电柱的高度。 还提供了其制造方法。

公开(公告)号：US09224731B2

公开(公告)日：2015-12-29

申请号：US14348581

申请日：2012-09-28

Applicant: Hiroshi Tamagawa ,  Yasuhiro Kondo ,  Yasuhiro Fuwa ,  Hiroyuki Okada ,  Eiji Nukaga ,  Katsuya Matsuura

Inventor： Hiroshi Tamagawa ,  Yasuhiro Kondo ,  Yasuhiro Fuwa ,  Hiroyuki Okada ,  Eiji Nukaga ,  Katsuya Matsuura

IPC: H01C10/00 ,  H01L27/06 ,  H01L27/08 ,  H01L21/308 ,  H01C1/14 ,  H01C13/02 ,  H01C17/242 ,  H01C17/00 ,  H05K3/34

CPC classification number: H01L28/20 ,  H01C1/14 ,  H01C13/02 ,  H01C17/006 ,  H01C17/242 ,  H01L21/3065 ,  H01L21/3083 ,  H01L27/0676 ,  H01L27/0802 ,  H05K3/3431 ,  H05K2201/10674

Abstract: [Theme] A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired.[Solution Means] A chip resistor 10 is arranged to have a resistor network 14 on a substrate. The resistor network 14 includes a plurality of resistor bodies R arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies R being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films C and fuse films F. By selectively fusing a fuse film F, a resistance unit can be electrically incorporated into the resistor network 14 or electrically separated from the resistor network to make the resistance value of the resistor network 14 the required resistance value.

Abstract translation: [主题]希望具有相同设计结构容易地容纳多种类型的所需电阻值的紧凑且精细的芯片电阻器。 [解决方案]芯片电阻器10布置成在基板上具有电阻网络14。 电阻网络14包括排列成矩阵并具有相等电阻值的多个电阻体R。 多个电阻单元分别由电连接的一个或多个电阻体R布置。 多种类型的电阻单元使用连接导体膜C和熔丝膜F以预定模式连接。通过选择性地熔化熔丝F，电阻单元可以电连接到电阻器网络14中或与电阻器网络电分离 使电阻网络14的电阻值成为所需电阻值。

公开(公告)号：US20150373849A1

公开(公告)日：2015-12-24

申请号：US14663447

申请日：2015-03-19

Applicant: IBIS Innotech Inc.

Inventor： Chih-Kung Huang ,  Wei-Jen Lai ,  Wen-Chun Liu

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K1/0373 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/04 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1715 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface. The conductive vias are disposed at the selective-electroplating epoxy compound to electrically connect the second patterned circuit layers to the corresponding metal studs.

Abstract translation: 封装结构包括选择性电镀环氧化合物，第一图案化电路层，第二图案化电路层，金属柱，接触焊盘和导电通孔。 选择性电镀环氧化合物包括空腔，第一表面和第二表面。 排列在第一表面上的空腔。 选择性电镀环氧化合物通过组合非导电金属络合物形成。 金属螺柱分别设置在空腔中并从第一表面突出。 第一图案化电路层直接设置在第一表面上。 选择性电镀环氧化合物暴露图案化电路层的顶表面。 顶面低于或与第一表面共面。 第二图案化电路层直接设置在第二表面上。 导电通孔设置在选择性电镀环氧化合物处，以将第二图案化电路层电连接到相应的金属螺柱。

公开(公告)号：US20150366080A1

公开(公告)日：2015-12-17

申请号：US14762899

申请日：2014-01-14

Applicant: DENSO CORPORATION

Inventor： Hirokazu SAITOH ,  Ichiro YOSHIDA

IPC: H05K3/40 ,  H05K3/46 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/4038 ,  H05K1/0216 ,  H05K3/0079 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/46 ,  H05K2201/09072 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/0594 ,  H05K2203/081 ,  H05K2203/1581 ,  Y10T29/49126

Abstract: In a method for manufacturing a multilayer substrate for having a BGA-type component thereon, a conductive through hole for restricting a signal interference and a resist film are formed on the multilayer substrate, an occurrence of a fault caused by a residual of a resist in the conductive through hole is reduced. In the method for manufacturing the multilayer substrate for having the BGA-type component thereon, a step of forming the resist film includes an applying step of applying a photosensitive resist to an entirety of a front surface portion of a base. The applying step is performed while restricting the resist from entering the conductive through hole by supplying a high pressure air to a rear surface of the base to pass through the conductive through hole using an air supply mechanism.

Abstract translation: 在其上具有BGA型成分的多层基板的制造方法中，在多层基板上形成用于限制信号干涉的导电性通孔和抗蚀剂膜，发生由抗蚀剂残留物引起的故障 导电通孔减少。 在其上具有BGA型部件的多层基板的制造方法中，形成抗蚀剂膜的步骤包括将感光性抗蚀剂涂布在基材的前表面部分的整体上的涂布步骤。 在使用空气供给机构通过向基座的后表面供给高压空气以通过导电性通孔的同时，进行施加步骤，同时限制抗蚀剂进入导电通孔。

公开(公告)号：US20150366061A1

公开(公告)日：2015-12-17

申请号：US14741011

申请日：2015-06-16

Applicant: IBIDEN CO., LTD.

Inventor： Kota NODA ,  Takeshi FURUSAWA

IPC: H05K1/14 ,  H05K1/02 ,  H05K3/10 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K1/03

CPC classification number: H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/0271 ,  H05K3/4697 ,  H05K2201/09827 ,  H05K2201/10674 ,  Y10T29/49158 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed wiring board includes a first circuit board having a first surface and a second surface, and a second circuit board having a third surface and a fourth surface and having a mounting area on the third surface of the second circuit board. The first circuit board is laminated on the third surface of the second circuit board such that the first surface of the first circuit board is in contact with the third surface of the second circuit board, the first circuit board includes reinforcing material and has an opening portion exposing the mounting area of the second circuit board, and the first circuit board and the second circuit board are formed such that a ratio H1/h1 is in a range of from 0.75 to 2.4, where H1 represents a thickness of the first circuit board and h2 represents a thickness of the second circuit board.

Abstract translation: 印刷电路板包括具有第一表面和第二表面的第一电路板和具有第三表面和第四表面的第二电路板，并且在第二电路板的第三表面上具有安装区域。 第一电路板层叠在第二电路板的第三表面上，使得第一电路板的第一表面与第二电路板的第三表面接触，第一电路板包括增强材料，并且具有开口部分 暴露第二电路板的安装区域，并且第一电路板和第二电路板形成为使得比率H1 / h1在0.75至2.4的范围内，其中H1表示第一电路板的厚度， h2表示第二电路板的厚度。

公开(公告)号：US09196402B2

公开(公告)日：2015-11-24

申请号：US12994143

申请日：2009-05-22

Applicant: Thomas Feichtinger ,  Guenter Engel ,  Axel Pecina

Inventor： Thomas Feichtinger ,  Guenter Engel ,  Axel Pecina

IPC: H05K1/03 ,  H01C1/084 ,  H01C7/10 ,  H01C7/12 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01C1/084 ,  H01C7/10 ,  H01C7/12 ,  H01L2224/48091 ,  H05K1/0203 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10106 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014

Abstract: An electric component assembly comprising a semiconductor component (1) and a carrier is specified, wherein the carrier contains a highly thermally conductive ceramic and is connected to a varistor body. Heat from the semiconductor component can be at least partially dissipated to the carrier (3) by means of the varistor body.

Abstract translation: 规定了包括半导体部件（1）和载体的电气部件组件，其中所述载体包含高导热性陶瓷，并连接到可变压敏电阻体。 来自半导体部件的热可以通过可变电阻体至少部分地耗散到载体（3）。

公开(公告)号：US09173282B2

公开(公告)日：2015-10-27

申请号：US13638536

申请日：2011-03-31

Applicant: Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

Inventor： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

IPC: H01R9/00 ,  H05K1/02 ,  H01L23/498 ,  H01L25/065 ,  H01R12/52 ,  H01R12/71 ,  H05K3/34 ,  H05K1/18 ,  H05K3/10 ,  H01L29/41 ,  H01L23/13 ,  H01L25/10 ,  H01L23/00

CPC classification number: H05K1/0213 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/413 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/45147 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81385 ,  H01L2224/81399 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/8185 ,  H01L2224/81897 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15791 ,  H01R12/52 ,  H01R12/714 ,  H05K1/18 ,  H05K3/107 ,  H05K3/3436 ,  H05K2201/0248 ,  H05K2201/0281 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/48

Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Abstract translation: 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（μm）的间距。 互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。 每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。 本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

公开(公告)号：US09167691B2

公开(公告)日：2015-10-20

申请号：US13863834

申请日：2013-04-16

Applicant: Identive Group, Inc.

Inventor： Werner Vogt

IPC: H05K1/11 ,  G06K19/077 ,  H05K3/32

CPC classification number: H05K1/112 ,  G06K19/07775 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/113 ,  H05K3/328 ,  H05K2201/10098 ,  H05K2201/10674 ,  Y10T29/49018 ,  Y10T29/49139 ,  H01L2924/00014

Abstract: Dual interface modules, and methods for manufacturing the same, are described. A substrate layer is provided with at least one dual interface section. At least two first through-holes are formed in the substrate in each dual interface section. A first connection element is arranged in each first through-hole. Each first connection element is connected to a contact pad that is arranged on a first side of the substrate. Each first connection element is connected to a connection pad that is arranged on a second side of the substrate. At least one electronic element is arranged on the second side of the substrate in each dual interface section. Two second through-holes are formed in the substrate in each dual interface section. Two soldering pads with a first side and a second side are arranged on the second side of the substrate layer.

Abstract translation: 描述了双接口模块及其制造方法。 衬底层设置有至少一个双接口部分。 在每个双界面部分中的基板中形成至少两个第一通孔。 第一连接元件布置在每个第一通孔中。 每个第一连接元件连接到布置在基板的第一侧上的接触焊盘。 每个第一连接元件连接到布置在基板的第二侧上的连接焊盘。 在每个双接口部分中，至少一个电子元件布置在衬底的第二侧上。 在每个双接口部分中的基板中形成两个第二通孔。 具有第一侧和第二侧的两个焊盘布置在衬底层的第二侧上。

公开(公告)号：US09159665B2

公开(公告)日：2015-10-13

申请号：US13645397

申请日：2012-10-04

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/60 ,  H01L23/488 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹