公开(公告)号：US20070074899A1

公开(公告)日：2007-04-05

申请号：US11505995

申请日：2006-08-18

Applicant: Hidenori Aonuma ,  Yasuhito Ohwaki

Inventor： Hidenori Aonuma ,  Yasuhito Ohwaki

IPC: H05K1/16

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/108 ,  H05K3/243 ,  H05K2201/0305 ,  H05K2201/09554 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A production method of a suspension board with circuit that can form the ground terminal for connection with the ground, while reducing the number of man-hour and complicated processes, and reduce production cost. After an insulating base layer is formed on a metal supporting board in such a manner that the base opening portion is formed in the metal supporting board, a conductive pattern comprising a ground wiring pattern and a signal wiring pattern is formed on the insulating base layer. Then, an insulating cover layer to cover the conductive pattern is formed on the insulating base layer in such a manner that a first cover opening portion and a second cover opening portion are formed in the insulating cover layer. Then, an electrolytic plating layer is formed on a surface of the ground terminal exposed from the first cover opening portion and on a surface of the ground connecting portion exposed from the second cover opening portion, feeding electric power from the ground wire. Thereafter, a metal filling layer is formed in the base opening portion so as to conduct the ground connecting portion and the metal supporting board.

Abstract translation: 具有电路的悬挂板的制造方法，其可以形成用于与地面连接的接地端子，同时减少工时数量和复杂的工艺，并降低生产成本。 在基板开口部分形成在金属支撑板上的金属支撑板上形成绝缘基底层之后，在绝缘基底层上形成包括接地布线图形和信号布线图形的导电图案。 然后，在绝缘基底层上形成覆盖导电图案的绝缘覆盖层，使得在绝缘覆盖层中形成第一盖开口部和第二盖开口部。 然后，在从第一盖开口部露出的接地端子的表面和从第二盖开口部露出的接地连接部的表面上形成电解镀层，从地线供电。 此后，在基部开口部分形成金属填充层，以便导通接地连接部分和金属支撑板。

公开(公告)号：US07195145B2

公开(公告)日：2007-03-27

申请号：US11180188

申请日：2005-07-13

Applicant: John M. Waldvogel ,  Herman J. Miller

Inventor： John M. Waldvogel ,  Herman J. Miller

IPC: B23K31/02 ,  B21D39/00 ,  H01L23/10 ,  H01L23/34

CPC classification number: B23K1/0016 ,  B23K2101/36 ,  H05K1/0206 ,  H05K1/0271 ,  H05K3/0061 ,  H05K3/305 ,  H05K3/341 ,  H05K3/386 ,  H05K2201/0305 ,  H05K2201/09318 ,  H05K2201/09554 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2201/10969 ,  H05K2203/0455 ,  Y02P70/611

Abstract: A method for assembling an electrical circuit apparatus that includes; a substrate having a top side, a ground layer, at least one thermal aperture, and at least one solder aperture; a heat sink; and an adhesive layer for mechanically coupling the heat sink to the ground layer of the substrate, the adhesive layer having at least one aperture wherein aligning the at least one substrate solder aperture with the at least one adhesive layer aperture enables solder wetting in a predetermined area between the heat sink and the ground layer of the substrate.

Abstract translation: 一种组装电路装置的方法，包括： 衬底，具有顶侧，接地层，至少一个热孔和至少一个焊接孔; 散热器 以及用于将散热器机械地耦合到基底的接地层的粘合剂层，所述粘合剂层具有至少一个孔，其中使所述至少一个基底焊接孔与所述至少一个粘合剂层孔对准使得焊料在预定区域中润湿 在散热片和衬底的接地层之间。

公开(公告)号：US07170012B2

公开(公告)日：2007-01-30

申请号：US11142399

申请日：2005-06-02

Applicant: Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H05K1/09

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board including a laminate of at least one insulating layer and at least one wiring layer. The wiring layer is formed by a composite member having a first metal layer and a second metal layer formed on one or both sides of the first metal layer. The first metal layer having a smaller coefficient of thermal expansion than the second metal layer. The second metal layer having a higher electric conductivity than the first metal layer. The insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer. A layer-to-layer interconnection portion is provided on the surface of the insulating layer and in the blind via-hole and is formed in the blind via-hole to be in contact with the surface of the second metal layer.

Abstract translation: 包括至少一个绝缘层和至少一个布线层的叠层的多层电路板。 布线层由具有形成在第一金属层的一侧或两侧上的第一金属层和第二金属层的复合构件形成。 第一金属层的热膨胀系数小于第二金属层。 第二金属层的导电率比第一金属层高。 绝缘层具有通过第二金属层的表面设置的底部的盲通孔。 在绝缘层的表面和盲通孔中设置层间互连部，并且形成在盲通孔中，与第二金属层的表面接触。

公开(公告)号：US20060213685A1

公开(公告)日：2006-09-28

申请号：US11442016

申请日：2006-05-26

Applicant: Alan Wang ,  Kevin Olson

Inventor： Alan Wang ,  Kevin Olson

IPC: H05K1/11

CPC classification number: H05K3/445 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/426 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes an electrically conductive sheet having an insulative coating surrounding the conductive sheet, with a surface of the insulative coating around an edge of the conductive sheet having an arcuate or rounded shape. At least one electrical conductor is conformally deposited on at least the rounded insulative coating around the edge of the conductive sheet and defined via photolithographic and metallization techniques. Each electrical conductor on the insulative coating thereon around the edge of the conductive sheet conforms to the arcuate or rounded shape of the insulative coating and, therefore, has an arcuate or rounded shape.

Abstract translation: 电路板包括具有围绕导电片的绝缘涂层的导电片，绝缘涂层的表面围绕导电片的边缘具有弓形或圆形形状。 至少一个电导体被共形沉积在导电片的边缘周围的至少圆形绝缘涂层上，并通过光刻和金属化技术限定。 导电片边缘周围的绝缘涂层上的每个电导体符合绝缘涂层的弧形或圆形形状，因此具有弓形或圆形形状。

公开(公告)号：US07095623B2

公开(公告)日：2006-08-22

申请号：US10445000

申请日：2003-05-27

Applicant: Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board having a high level of reliability in terms of electric connection against temperature changes caused by the actual operation of electronic equipment, a manufacturing process, a substrate for multilayer circuitry, and an electronic apparatus. The multilayer circuit board comprises a laminate of at least one insulating layer and at least one wiring layer, wherein the wiring layer is formed by a composite member comprising a first metal layer and a second metal layer formed on one or both sides of the first metal layer, the first metal layer having a smaller coefficient of thermal expansion than the second metal layer, the second metal layer having a higher electric conductivity than the first metal layer, wherein the insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer, the circuit board further comprising a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole, wherein the layer-to-layer interconnection portion in the blind via-hole is formed in such a manner as to be in contact with the surface of the second metal layer.

公开(公告)号：US07084509B2

公开(公告)日：2006-08-01

申请号：US10263909

申请日：2002-10-03

Applicant: Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

Inventor： Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract translation: 通过在层叠到用作接地平面或电源平面的导电金属芯的第一介电层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。 通过延伸到芯的电介质层提供孔。 使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。 金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。 第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。 该第二通孔可以由常规电镀技术形成。 可以以这种方式组装具有堆叠的盲孔的多个电介质层。

公开(公告)号：US07059049B2

公开(公告)日：2006-06-13

申请号：US10253725

申请日：2002-09-24

Applicant: Donald S. Farquhar ,  James D. Herard ,  Michael J. Klodowski ,  David Questad ,  Der-jin Woan

Inventor： Donald S. Farquhar ,  James D. Herard ,  Michael J. Klodowski ,  David Questad ,  Der-jin Woan

IPC: H01K3/10

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/068 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract translation: 电子封装和形成方法。 提供具有第一和第二相对表面的导热层。 第一电介质层在加压下被层压在导热层的第一相对表面上，温度在最低温度T 1 1MIN和最高温度T 1MAX之间。 在层压之后，T 1MAX 3将第一介电层的延展性约束至少为D 1。 T 1MAX取决于D 1和在由第一介电层组成的第一电介质材料上。 在加压下将第二电介质层在导热层的第二相对表面上，在最低温度T 2 M 2 N 2和最大温度T 2 MAX之间的温度下层压。 在层压之后，T 2MAX 2将第二介电层的延展性约束为至少D 2。 T 2MAX取决于D 2和在由第二介电层组成的第二电介质材料上。

公开(公告)号：US06998540B2

公开(公告)日：2006-02-14

申请号：US10426326

申请日：2003-04-29

Applicant: Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

Inventor： Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

IPC: H01R12/04

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/0979 ,  H05K2201/09854 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.

公开(公告)号：US06981320B2

公开(公告)日：2006-01-03

申请号：US10748478

申请日：2003-12-29

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01K3/10

CPC classification number: H05K3/4652 ,  H05K1/056 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/4614 ,  H05K2201/09554 ,  H05K2201/10378 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A circuit board and a fabricating process thereof is provided. The present invention employs a core layer as a base layer, wherein the core layer is a core conducting layer, or is a core dielectric layer having two conducting layers. By using this core layer and two patterned conductive layers, a three-conducting-layer circuit board or a four-conducting-layer circuit board is fabricated. Furthermore, both circuit boards can be used as circuit board units to fabricate circuit boards having more than four conducting layers. The present invention adopts lamination processes and equipment instead of using complicated build-up process. Therefore, the present invention effectively reduces the production costs and simplifies the process cycle for fabricating circuit boards, and is suitable for mass production.

Abstract translation: 提供电路板及其制造方法。 本发明采用芯层作为基层，其中芯层是芯导电层，或是具有两个导电层的芯介质层。 通过使用该芯层和两个图案化的导电层，制造三导电层电路板或四导电层电路板。 此外，两个电路板可以用作电路板单元以制造具有多于四个导电层的电路板。 本发明采用层压工艺和设备，而不是采用复杂的堆积工艺。 因此，本发明有效地降低了制造成本，并且简化了制造电路板的工艺循环，并且适合于批量生产。

公开(公告)号：US06951707B2

公开(公告)日：2005-10-04

申请号：US10184387

申请日：2002-06-27

Applicant: Alan E. Wang ,  Kevin C. Olson

Inventor： Alan E. Wang ,  Kevin C. Olson

IPC: H05K1/05 ,  H05K3/00 ,  H05K3/06 ,  H05K3/44 ,  H05K3/46 ,  G03F7/00

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract translation: 提供了一种用于创建电路组件的通孔的方法，包括以下步骤：（a）将可固化涂料组合物施加到基底上，其中一些或全部导电，以在其上形成未固化的涂层; （b）在未固化的涂层上涂覆抗蚀剂; （c）在预定位置对抗蚀剂进行成像; （d）显影抗蚀剂以暴露未固化涂层的预定区域; （e）去除未固化涂层的暴露区域; 和（f）将步骤（e）的涂布基材加热到足以固化涂层的温度和时间。还公开了一种制造电路组件的方法。