公开(公告)号：US08654539B2

公开(公告)日：2014-02-18

申请号：US13389364

申请日：2010-08-04

Applicant: Naoya Nakanishi

Inventor： Naoya Nakanishi

IPC: H05K1/18 ,  H01L21/02

CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10674

Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50.

Abstract translation: 本发明的目的是提供一种通过确保即使在通孔导体组中发生故障连接而产生电位的路径也可以提高连接可靠性的电容器配线布线基板。 在本发明的电容器配线基板中，电容器50容纳在芯体11中，并且在电容器50的上侧和下侧分别形成有第一和第二积累层12和13。

公开(公告)号：US20140034357A1

公开(公告)日：2014-02-06

申请号：US13955474

申请日：2013-07-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang-Kyung LEE ,  Hee-Kyoung Lee ,  Dong-Hwan Lee ,  Kyung-Sang Lim

IPC: H05K1/02

CPC classification number: H05K1/0242 ,  H05K1/0219 ,  H05K1/0233 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0979

Abstract: A printed circuit board disclosed. One embodiment of the present invention provides a printed circuit board that includes: an insulation layer having multiple layers of circuit wirings formed therein; a via formed along a perimeter of the insulation layer and configured for connecting circuit wirings formed on different layers of the insulation layer, the via being formed in such a way that an inside thereof is hollow; and an electromagnetic wave absorbing part contained in the via.

Abstract translation: 公开了印刷电路板。 本发明的一个实施例提供了一种印刷电路板，其包括：绝缘层，其中形成有多层电路布线; 沿绝缘层的周边形成的通孔，其被构造用于连接形成在绝缘层的不同层上的电路布线，所述通孔以使其内部为中空的方式形成; 以及包含在通孔中的电磁波吸收部。

公开(公告)号：US20130299221A1

公开(公告)日：2013-11-14

申请号：US13644910

申请日：2012-10-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Jae OH ,  Yoon Hyuck CHOI ,  Bong Gyun KIM ,  Joo Yong KIM

IPC: H05K1/11 ,  H05K3/10 ,  H05K1/02

CPC classification number: H05K1/141 ,  G01R1/07378 ,  H05K1/0218 ,  H05K1/0306 ,  H05K1/11 ,  H05K2201/09609

Abstract: There is provided a space transformer for a probe card, including: a substrate having a first surface and a second; a plurality of first pads formed on the first surface to be spaced apart from each other and connected to a printed circuit board of a probe card; a plurality of second pads formed on the second surface in positions corresponding to those of the first pads and receiving external electrical signals applied thereto; a plurality of via electrodes penetrating through the substrate and respectively connected to the plurality of first pads and the plurality of second pads formed in the positions corresponding to each other; a ground layer formed to cover the second surface and provided with a plurality of second pad exposure holes; and an insulating layer formed to cover the ground layer and the plurality of second pads.

Abstract translation: 提供了一种用于探针卡的空间变压器，包括：具有第一表面和第二表面的基底; 多个第一焊盘，形成在第一表面上以彼此间隔开并连接到探针卡的印刷电路板; 多个第二焊盘，其形成在与第一焊盘相对应的位置的第二表面上，并且接收施加到其上的外部电信号; 多个通孔，穿过基板并分别连接到形成在彼此对应的位置的多个第一焊盘和多个第二焊盘; 形成为覆盖所述第二表面并设置有多个第二焊盘曝光孔的接地层; 以及形成为覆盖所述接地层和所述多个第二焊盘的绝缘层。

公开(公告)号：US08544169B2

公开(公告)日：2013-10-01

申请号：US12875644

申请日：2010-09-03

Applicant: Takamasa Takano

Inventor： Takamasa Takano

IPC: H01K3/10

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/01079

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

Abstract translation: 一种制造通孔电极基板的方法包括在基板上形成多个通孔，通过在多个通孔中填充导电材料形成多个通孔电极，在一个通孔上形成第一绝缘层 在所述第一绝缘层上形成多个第一开口，所述多个第一开口将与所述多个通孔电极中的每一个相对应的多个通孔电极暴露在所述第一绝缘层上，并且使用所述关系来校正所述多个第一开口的位置 在多个通孔中的倾斜通孔的打开位置的测量距离值的偏移量与多个通孔中的倾斜通孔的打开位置的设计距离值之间， 相对于基板的中心位置。

公开(公告)号：US08493269B2

公开(公告)日：2013-07-23

申请号：US12878268

申请日：2010-09-09

Applicant: Soo-Yong Jang ,  Austin Kim ,  Jae-Ho Lee ,  Young-Soon Lee ,  Ui-Jung Kim

Inventor： Soo-Yong Jang ,  Austin Kim ,  Jae-Ho Lee ,  Young-Soon Lee ,  Ui-Jung Kim

IPC: H01Q1/38

CPC classification number: H05K1/024 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/52 ,  H01Q17/00 ,  H05K1/0253 ,  H05K2201/09036 ,  H05K2201/09309 ,  H05K2201/09609

Abstract: A magnetodielectric substrate includes a first dielectric layer, a second dielectric layer, conductive patterns, and a plurality of air vias. The first dielectric layer has a predetermined height, and the second dielectric layer is stacked on the first dielectric layer. Conductive patterns are coated on an upper surface and a lower surface of one of the first and second dielectric layers. A plurality of air vias is formed with a predetermined diameter and a predetermined interval such that they pass through up to the conductive patterns of the upper and lower surfaces from the dielectric layer on which the conductive patterns are coated.

Abstract translation: 磁电介质基板包括第一电介质层，第二电介质层，导电图案和多个空气通孔。 第一电介质层具有预定的高度，并且第二电介质层堆叠在第一电介质层上。 导电图案涂覆在第一和第二电介质层之一的上表面和下表面上。 多个空气通孔以预定直径和预定间隔形成，使得它们从其上涂覆导电图案的电介质层通过到上表面和下表面的导电图案。

公开(公告)号：US20130175077A1

公开(公告)日：2013-07-11

申请号：US13345247

申请日：2012-01-06

Applicant: Hyunjun Kim ,  Jeffrey S. Conger ,  Gregory E. Scott

Inventor： Hyunjun Kim ,  Jeffrey S. Conger ,  Gregory E. Scott

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0225 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.

公开(公告)号：US20130099876A1

公开(公告)日：2013-04-25

申请号：US13806824

申请日：2010-06-30

Applicant: Taras Kushta

Inventor： Taras Kushta

IPC: H01P1/213

CPC classification number: H01P1/20 ,  H01P1/203 ,  H05K1/0222 ,  H05K1/0233 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0979

Abstract: A filter of the present invention includes a plurality of via structures with a multilayer substrate. Each of the plurality of via structures includes first, second and third functional sections. One end of a signal via of the first functional section is connected to one end of a signal via of the second functional section and another end of the signal via of the second functional section is connected to two signal vias of the third functional section. Those signal vias are surrounded by a plurality of ground vias. Input and output ports of the filter are connected to another end of the signal via of each first functional section.

Abstract translation: 本发明的过滤器包括具有多层基板的多个通孔结构。 多个通孔结构中的每一个包括第一，第二和第三功能部分。 第一功能部的信号通路的一端连接到第二功能部的信号通路的一端，第二功能部的信号通路的另一端连接到第三功能部的两个信号通路。 那些信号通道被多个接地通孔包围。 滤波器的输入和输出端口连接到每个第一功能部分的信号通道的另一端。

公开(公告)号：US20120031655A1

公开(公告)日：2012-02-09

申请号：US13275808

申请日：2011-10-18

Applicant: Kevin C. Olson ,  Alan G. Wang

Inventor： Kevin C. Olson ,  Alan G. Wang

IPC: H05K1/09 ,  H05K3/00 ,  H05K1/02

CPC classification number: H01L21/486 ,  C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  H01L2924/00

Abstract: A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.

Abstract translation: 提供了一种用于制造多层电路组件的工艺。 该方法包括（a）提供基底，其至少一个区域包括通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的多个通孔区域; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; （c）以预定图案去除所述电介质涂层以暴露所述基板的部分; （d）将金属层施加到所有表面以形成通过和/或导电芯的金属化通孔; （e）在所述金属层上施加抗蚀剂以在其上形成感光层; （f）在预定位置的成像抗蚀剂; （g）显影抗蚀剂以露出金属层的选定区域; 和（h）蚀刻金属的未覆盖区域以形成通过金属化通孔连接的电路图案。

公开(公告)号：US20110241794A1

公开(公告)日：2011-10-06

申请号：US12895347

申请日：2010-09-30

Applicant: Hsueh-Yuan Pao ,  Gerardo Aguirre ,  Paul Sargis

Inventor： Hsueh-Yuan Pao ,  Gerardo Aguirre ,  Paul Sargis

IPC: H03H7/38 ,  H01P5/08 ,  H01R9/00

CPC classification number: H01R24/50 ,  H05K1/0253 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/10189 ,  H05K2201/10446

Abstract: An impedance matching ground plane step, in conjunction with a quarter wave transformer section, in a printed circuit board provides a broadband microwave matching transition from board connectors or other elements that require thin substrates to thick substrate (>quarter wavelength) broadband microwave (millimeter wave) devices. A method of constructing microwave and other high frequency electrical circuits on a substrate of uniform thickness, where the circuit is formed of a plurality of interconnected elements of different impedances that individually require substrates of different thicknesses, by providing a substrate of uniform thickness that is a composite or multilayered substrate; and forming a pattern of intermediate ground planes or impedance matching steps interconnected by vias located under various parts of the circuit where components of different impedances are located so that each part of the circuit has a ground plane substrate thickness that is optimum while the entire circuit is formed on a substrate of uniform thickness.

Abstract translation: 与印刷电路板中的四分之一波长变压器部分的阻抗匹配接地平面步骤提供了从板连接器或需要薄衬底到厚衬底（>四分之一波长）宽带微波（毫米波）的其它元件的宽带微波匹配过渡 ） 设备。 一种在均匀厚度的衬底上构造微波和其它高频电路的方法，其中电路由具有不同阻抗的多个互连元件形成，该互连元件分别需要不同厚度的衬底，通过提供均匀厚度的衬底， 复合或多层基材; 并且形成中间接地面或者阻抗匹配步骤的图案，所述中间接地平面或阻抗匹配步骤通过位于电路各部分的不同阻抗位置的通孔相互连接，使得电路的每个部分具有最佳的接地平面衬底厚度，而整个电路为 形成在均匀厚度的基底上。

公开(公告)号：US20110203842A1

公开(公告)日：2011-08-25

申请号：US12798217

申请日：2010-03-31

Applicant: James V. Russell

Inventor： James V. Russell

IPC: H05K1/11 ,  H05K13/00

CPC classification number: H05K1/0222 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/42 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09727 ,  H05K2201/09809 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A method and a structure for a coaxial via that extend along the entire length of a signal via in a printed circuit board. Signal integrity is improved by providing ground shield for the entire length of the coaxial via. The ground shielding can be implemented by either providing ground cage vias around a signal via and routing a trace to the signal via on a built up layer or by providing a semi circle ground trench through a build up layer to permit a trace access to the signal via.

Abstract translation: 一种用于沿着印刷电路板中的信号通道的整个长度延伸的同轴通孔的方法和结构。 通过为同轴通孔的整个长度提供接地屏蔽来改善信号完整性。 接地屏蔽可以通过在信号通孔周围提供接地保持架通孔，并将迹线路由到建立层上的信号通道或者通过建立层提供半圆接地沟槽来实现，以允许对信号进行跟踪访问 通过。