公开(公告)号：US11550325B2

公开(公告)日：2023-01-10

申请号：US16898308

申请日：2020-06-10

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler ,  Alejandro Troccoli

IPC: G05D1/02 ,  G01S13/931 ,  G05D1/00 ,  B60W60/00 ,  G05B13/02

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

公开(公告)号：US20220406371A1

公开(公告)日：2022-12-22

申请号：US17350973

申请日：2021-06-17

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang ,  Stefan P. Sywyk

IPC: G11C11/418

Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

公开(公告)号：US11442795B2

公开(公告)日：2022-09-13

申请号：US16567993

申请日：2019-09-11

Applicant: NVIDIA Corp.

Inventor： Daniel Robert Johnson ,  Jack Choquette ,  Oliver Giroux ,  Michael Patrick McKeown ,  Mark Stephenson ,  Sana Damani

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/48

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

公开(公告)号：US11411563B1

公开(公告)日：2022-08-09

申请号：US17184396

申请日：2021-02-24

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: H03K19/17768 ,  H04L9/32 ,  H04L9/08 ,  H03K19/173 ,  H03K19/17748 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/177

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

公开(公告)号：US20220095017A1

公开(公告)日：2022-03-24

申请号：US17539947

申请日：2021-12-01

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L12/743 ,  H04N21/43 ,  H04L12/841 ,  H04L12/733 ,  H04N21/234

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US20220026715A1

公开(公告)日：2022-01-27

申请号：US16937235

申请日：2020-07-23

Applicant: NVIDIA Corp.

Inventor： Jui-Hsien Wang ,  Ward Lopes ,  Rachel Anastasia Brown ,  Peter Shirley

IPC: G02B27/01 ,  G06T15/00 ,  G06T1/20 ,  G06F16/901 ,  H04L9/06

Abstract: The computational scaling challenges of holographic displays are mitigated by techniques for generating holograms that introduce foveation into a wave front recording planes approach to hologram generation. Spatial hashing is applied to organize the points or polygons of a display object into keys and values.

公开(公告)号：US11212073B2

公开(公告)日：2021-12-28

申请号：US16802437

申请日：2020-02-26

Applicant: NVIDIA Corp.

Inventor： Pervez Mirza Aziz ,  Vishnu Balan ,  Viswanath Annampedu

IPC: H04L7/033 ,  H04L25/03 ,  H04L7/00

Abstract: A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

公开(公告)号：US11169779B2

公开(公告)日：2021-11-09

申请号：US16803795

申请日：2020-02-27

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/501 ,  G06F9/30 ,  G06F7/575 ,  G06F7/509 ,  G06F7/533 ,  H03K19/21 ,  G06F7/53

Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

公开(公告)号：US20210295169A1

公开(公告)日：2021-09-23

申请号：US17231866

申请日：2021-04-15

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06N3/08 ,  G06T1/20 ,  G06T11/20 ,  G06N3/04 ,  G06F30/323

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US20210281067A1

公开(公告)日：2021-09-09

申请号：US16812048

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Jauwen Chen ,  Sunitha Venkataraman ,  Ting Ku

IPC: H02H9/04 ,  H01L27/02

Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.