公开(公告)号：US20180054889A1

公开(公告)日：2018-02-22

申请号：US15603326

申请日：2017-05-23

Applicant: Sierra Circuits, Inc.

Inventor： Kenneth S. BAHL ,  Konstantine KARAVAKIS

IPC: H05K1/03 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K1/11 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02

CPC classification number: H05K1/0313 ,  H05K1/0296 ,  H05K1/0353 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/038 ,  H05K1/09 ,  H05K1/115 ,  H05K3/18 ,  H05K3/181 ,  H05K3/182 ,  H05K3/387 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4632 ,  H05K2201/0209 ,  H05K2201/0227 ,  H05K2201/0242 ,  H05K2201/0376 ,  H05K2203/0716

Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

公开(公告)号：US09899235B2

公开(公告)日：2018-02-20

申请号：US15293858

申请日：2016-10-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Ying-Chou Tsai ,  Sheng-Che Huang

IPC: H01L21/48 ,  H01L23/00 ,  H05K3/20 ,  H05K3/34 ,  H05K3/40 ,  H01L23/498 ,  H01L21/683 ,  H05K3/06 ,  H05K3/46

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81193 ,  H05K3/064 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2201/0376 ,  Y02P70/613 ,  Y10T29/49158

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

公开(公告)号：US09839138B2

公开(公告)日：2017-12-05

申请号：US14481273

申请日：2014-09-09

Applicant: Inktec Co., Ltd.

Inventor： Kwang Choon Chung ,  Ji Hoon Yoo ,  Su-Han Kim ,  Byung Hun Kim

IPC: H05K3/12 ,  H05K1/09 ,  H05K3/10

CPC classification number: H05K3/1258 ,  C23C18/165 ,  C23C18/1868 ,  C23C18/204 ,  H05K1/092 ,  H05K1/097 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/245 ,  H05K2201/0112 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0568 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1126

Abstract: The present invention relates to a method for fabricating blackened conductive patterns, which includes (i) forming a resist layer on a non-conductive substrate; (ii) forming fine pattern grooves in the resist layer using a laser beam; (iii) forming a mixture layer containing a conductive material and a blackening material in the fine pattern grooves; and (iv) removing the resist layer remained on the non-conductive substrate.

公开(公告)号：US09832883B2

公开(公告)日：2017-11-28

申请号：US13870644

申请日：2013-04-25

Applicant: Intel Corporation

Inventor： Qinglei Zhang

IPC: H05K7/10 ,  H05K7/12 ,  H05K3/24 ,  H05K3/28 ,  H01L23/13 ,  H01L21/48 ,  H05K3/34 ,  H01L23/00

CPC classification number: H05K3/244 ,  H01L21/4857 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2924/12042 ,  H05K3/282 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/025 ,  H05K2203/1476 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

公开(公告)号：US20170256479A1

公开(公告)日：2017-09-07

申请号：US15600793

申请日：2017-05-22

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/495 ,  H01L23/60

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/053 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/60 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.

公开(公告)号：US20170148724A1

公开(公告)日：2017-05-25

申请号：US15351838

申请日：2016-11-15

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： CHUN-HSIEN YU ,  PAO-HUNG CHOU

IPC: H01L23/498 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49894 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K3/28 ,  H05K2201/0376

Abstract: This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed on the rigid dielectric material layer, and a first flexible dielectric material layer formed on the first wiring layer.

公开(公告)号：US09568156B2

公开(公告)日：2017-02-14

申请号：US14133822

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ariyoshi Tetsuo ,  Cheon Ho Park ,  Jong Pil Won ,  Ji Hoon Yun ,  Jun Ho Jung

IPC: F21V5/04 ,  F21V5/02 ,  H01L33/38 ,  H01L33/44 ,  H05K1/02 ,  H05K1/18 ,  H05K3/10 ,  H05K3/30 ,  H05K3/44 ,  F21Y101/00

CPC classification number: F21K9/64 ,  F21K9/27 ,  F21K9/65 ,  F21K9/69 ,  F21V5/02 ,  F21V5/043 ,  F21Y2101/00 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L33/38 ,  H01L33/44 ,  H01L2224/13 ,  H01L2224/48091 ,  H05K1/021 ,  H05K1/0256 ,  H05K1/189 ,  H05K3/107 ,  H05K3/305 ,  H05K3/44 ,  H05K2201/0338 ,  H05K2201/0358 ,  H05K2201/0376 ,  H05K2201/09154 ,  H05K2201/098 ,  H05K2201/10106 ,  H05K2203/0139 ,  H05K2203/025 ,  H01L2924/00014

Abstract: A light source module including a substrate, a plurality of light emitting devices installed on the substrate, and a plurality of lenses installed on the substrate to cover the plurality of light emitting devices, respectively, and each of the plurality of lenses having a pair of open end portions facing one another, the plurality of lenses arranged such that an open end portion of one lens faces an opened end portion of an adjacent lens is provided.

Abstract translation: 一种光源模块，包括基板，安装在基板上的多个发光装置，以及分别安装在基板上以覆盖多个发光装置的多个透镜，并且多个透镜中的每一个具有一对 所述多个透镜被设置为使得一个透镜的开口端部面向相邻透镜的开口端部。

公开(公告)号：US09510457B2

公开(公告)日：2016-11-29

申请号：US14004560

申请日：2012-07-30

Applicant: Jae Wook Kang ,  Do Geun Kim ,  Jong Kuk Kim ,  Sung Hun Jung ,  Seunghun Lee

Inventor： Jae Wook Kang ,  Do Geun Kim ,  Jong Kuk Kim ,  Sung Hun Jung ,  Seunghun Lee

IPC: H05K3/00 ,  H05K1/03 ,  H05K3/20 ,  H05K1/02 ,  H05K3/10

CPC classification number: H05K3/0041 ,  H05K1/0283 ,  H05K1/03 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/20 ,  H05K3/207 ,  H05K2201/0326 ,  H05K2201/0376 ,  H05K2201/10037 ,  H05K2201/10098 ,  H05K2201/10128 ,  H05K2203/0139 ,  H05K2203/016 ,  H05K2203/0264 ,  H05K2203/095

Abstract: Disclosed are methods of manufacturing a metal wiring buried flexible substrate by using plasma and flexible substrates manufactured by the same. The method includes pre-treating a substrate by irradiating the plasma on the surface of the substrate (Step 1), forming a metal wiring on the pre-treated substrate in Step 1 (Step 2), forming a metal wiring buried polymer layer by coating a curable polymer on the substrate including the metal wiring formed thereon in Step 2 and curing (Step 3), and separating the polymer layer formed in Step 3 from the substrate in Step 1 (Step 4). The metal wiring may be inserted into the flexible substrate, and the resistance of the wiring may be decreased. The metal wiring may be clearly separated from the substrate, and impurities on the substrate surface may be clearly removed. The flexible substrate may be easily separated by applying only physical force.

Abstract translation: 公开了通过使用由其制造的等离子体和柔性基板来制造金属布线掩埋的柔性基板的方法。 该方法包括通过在基板表面照射等离子体来预处理基板（步骤1），在步骤1（步骤2）中在预处理基板上形成金属布线，通过涂布形成金属布线掩埋的聚合物层 在步骤2中，将包含形成在其上的金属布线的固化性聚合物固化（步骤3），并且在步骤1（步骤4）中将步骤3中形成的聚合物层与基板分离。 可以将金属布线插入到柔性基板中，并且可以减小布线的电阻。 金属布线可以从衬底清楚地分离，并且可以清楚地去除衬底表面上的杂质。 柔性基板可以通过仅施加物理力而容易地分离。

公开(公告)号：US20160295684A1

公开(公告)日：2016-10-06

申请号：US15184511

申请日：2016-06-16

Applicant: LG INNOTEK CO., LTD.

Inventor： Yong Seok Cho ,  Chang Sung Kim

IPC: H05K1/02

CPC classification number: H05K1/0203 ,  H05K1/0209 ,  H05K1/0227 ,  H05K1/09 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/09881

Abstract: Disclosed is a printed circuit board. The printed circuit board includes an insulating layer, a copper foil formed on the insulating layer and formed therein with a groove to expose a portion of a top surface of the insulating layer, and a thermal conductive layer filled in the groove.

公开(公告)号：US20160278206A1

公开(公告)日：2016-09-22

申请号：US15165458

申请日：2016-05-26

Applicant: SIERRA CIRCUITS, INC.

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

IPC: H05K1/03 ,  H05K3/40 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4038 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0154 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2203/025 ,  H05K2203/0716 ,  H05K2203/107

Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.

Abstract translation: 印刷电路板包括层叠基板。 层压基板包括抵抗金属电镀的催化材料，除了催化材料的表面被烧蚀之外。 金属痕迹形成在层压基板内的痕迹通道内。 通道延伸到催化材料的表面之下。