公开(公告)号：US06707682B2

公开(公告)日：2004-03-16

申请号：US09956909

申请日：2001-09-21

Applicant: Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

Inventor： Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

IPC: H05K118

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed.

Abstract translation: 通过将电源层的电位波动相对于在切换IC器件等而发生的接地层的电位波动转换为基底中的焦耳热而不使用任何部件作为对策来实现高安装密度的低EMI电路 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。

公开(公告)号：US06680218B2

公开(公告)日：2004-01-20

申请号：US10371659

申请日：2003-02-21

Applicant: Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L2144

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US20030218878A1

公开(公告)日：2003-11-27

申请号：US10417896

申请日：2003-04-16

Applicant: Permlight Products, Inc.

Inventor： Jagath Swaris ,  Scott Van Ness

IPC: F21V033/00

CPC classification number: F21V29/70 ,  F21S4/20 ,  F21V17/007 ,  F21Y2115/10 ,  G09F13/0404 ,  G09F13/22 ,  H01L25/13 ,  H01L33/64 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/0058 ,  H05K2201/10106 ,  H05K2201/10446 ,  Y10S362/80 ,  H01L2924/00014

Abstract: A modular light emitting diode (LED) mounting configuration is provided including a light source module having a plurality of pre-packaged LEDs arranged in a serial array. The module includes a heat conductive body portion adapted to conduct heat generated by the LEDs to an adjacent heat sink. A heat conductive adhesive tape connects the LED module to the mount surface. As a result, the LEDs are able to be operated with a higher current than normally allowed. Thus, brightness and performance of the LEDs is increased without decreasing the life expectancy of the LEDs. A plurality of such LED modules can be pre-wired together in a substantially continuous fashion and provided in a dispenser, such as a roll or box. Thus, to install a plurality of such LED modules, a worker simply pulls modules from the dispenser as needed, secures the appropriate number of modules in place, and connects the assembled modules to a power source.

公开(公告)号：US06636429B2

公开(公告)日：2003-10-21

申请号：US09957001

申请日：2001-09-20

Applicant: Douglas Maly ,  Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett

Inventor： Douglas Maly ,  Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett

IPC: H05K900

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A high frequency, low impedance network is integrated into the substrate level of a power module for the reduction of electromagnetic interference (“EMI”). In one embodiment, capacitance is electrically connected to at least one of the positive conducting layer in a substrate or the negative conducting layer in a substrate and a ground. Integrating a capacitive network of low stray inductance in a substrate of a power module allows relatively small, inexpensive capacitors to be used.

公开(公告)号：US20030107452A1

公开(公告)日：2003-06-12

申请号：US10342803

申请日：2003-01-15

Applicant: Sun Microsystems, Inc.

Inventor： Istvan Novak

IPC: H03H007/38

CPC classification number: H05K1/0231 ,  H05K1/0234 ,  H05K1/113 ,  H05K1/167 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10446 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where nnull2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res. The mounted resistance Rm of each of the n capacitors includes an electrical resistance of the corresponding electrical resistance element. The electrical power distribution structure achieves an electrical impedance Z at the resonant frequency fm-res of the capacitors. The mounted resistance Rm of each of the n capacitors is substantially equal to (nnullZ). The mounted inductance Lm of each of the n capacitors is less than or equal to (0.2nullnnullnull0nullh), where null0 is the permeability of free space, and h is a distance between the planar conductors.

公开(公告)号：US20030040218A1

公开(公告)日：2003-02-27

申请号：US10213871

申请日：2002-08-06

Inventor： Martin Gollhofer ,  Roland Etzkom ,  Wolfgang Zeeb ,  Wolfgang Hutt ,  Michael Stache

IPC: H01R013/60 ,  H01R013/66

CPC classification number: H01R12/7052 ,  H05K3/306 ,  H05K2201/09081 ,  H05K2201/10189 ,  H05K2201/10424 ,  H05K2201/10446 ,  H05K2201/10575 ,  H05K2201/10598

Abstract: An electrical connector is constructed for ease of fixing a sheet metal solder plate (25) to the bottom surface portion (70) of the connector insulator frame (12), so the solder plate can be soldered to one or more traces on a circuit board to hold down the frame. The frame has downwardly extending pegs (33-35) and the solder plate has corresponding peg-receiving holes (28-30). The mount plate forms at least one tongue (50, 51) at each of its holes, each tongue projecting against one of the pegs to form an interference fit against the peg that prevents removable of the solder plate from the insulator pegs. Each peg has a vertical slot (38, 39) that receives a nose (50, 51) at the end of the tongue.

Abstract translation: 电连接器被构造为便于将金属板焊接板（25）固定到连接器绝缘体框架（12）的底表面部分（70），使得焊接板可以焊接到电路板上的一个或多个迹线 按住框架。 框架具有向下延伸的销钉（33-35），并且焊接板具有对应的钉接收孔（28-30）。 安装板在其每个孔处形成至少一个舌部（50,51），每个舌片突出抵靠其中一个栓钉，以形成与栓钉的过盈配合，从而防止焊接板从绝缘钉上移除。 每个钉具有在舌头末端接收鼻子（50,51）的垂直槽（38,39）。

公开(公告)号：US06525622B1

公开(公告)日：2003-02-25

申请号：US09715723

申请日：2000-11-17

Applicant: Istvan Novak ,  Valerie A. St. Cyr ,  Merle Tetreault ,  Daniel C. Irish

Inventor： Istvan Novak ,  Valerie A. St. Cyr ,  Merle Tetreault ,  Daniel C. Irish

IPC: H03H738

CPC classification number: H05K1/0231 ,  H05K1/0234 ,  H05K1/113 ,  H05K1/167 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10446 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res. The mounted resistance Rm of each of the n capacitors includes an electrical resistance of the corresponding electrical resistance element. The electrical power distribution structure achieves an electrical impedance Z at the resonant frequency fm-res of the capacitors. The mounted resistance Rm of each of the n capacitors is substantially equal to (n·Z). The mounted inductance Lm of each of the n capacitors is less than or equal to (0.2·n·&mgr;0·h), where &mgr;0 is the permeability of free space, and h is a distance between the planar conductors.

Abstract translation: 通过电耦合多个旁路电容器和在平面导体之间串联的相应的电阻元件来实现电力分配结构的平行平面导体之间的电阻抗的期望值的装置和方法。 该方法包括基于仿真结果的旁路电容器选择标准和电阻确定标准。 通过这些方法之一产生的示例性配电结构包括一对由电介质层分开的平行平面导体，n个分立的电容器和n个电阻元件，其中n≥2。 n个分立电阻元件中的每一个与平面导体之间的n个分立电容器中的相应一个耦合。 n个电容器具有基本相同的电容C，安装电阻Rm，安装电感Lm和安装的谐振频率fm-res。 n个电容器中的每一个的安装电阻Rm包括相应的电阻元件的电阻。 电力分配结构在电容器的谐振频率fm-res处实现电阻抗Z。 n个电容器中的每一个的安装电阻Rm基本上等于（n.Z）。 n个电容器中的每一个的安装电感Lm小于或等于（0.2.n.mu.h），其中μ0是自由空间的磁导率，h是平面导体之间的距离。

公开(公告)号：US06386708B1

公开(公告)日：2002-05-14

申请号：US09342599

申请日：1999-06-29

Applicant: Jun Arai ,  Akira Tominaga ,  Masayuki Suyama

Inventor： Jun Arai ,  Akira Tominaga ,  Masayuki Suyama

IPC: G03B2100

CPC classification number: H04N9/3105 ,  H04N9/3144 ,  H05K1/141 ,  H05K1/182 ,  H05K3/368 ,  H05K2201/10106 ,  H05K2201/10446

Abstract: A projection display device permits extension of a space for mounting an electronic component on a control circuit substrate. The projection display device includes a control circuit substrate on which a control circuit is mounted for controlling driving of each of apparatuses in the device according to the input operation signal from an external light receiving unit; and a signal transmission circuit comprising a light emitting element and a light receiving element and provided in a conduction passage on the circuit substrate. The control circuit substrate includes a first circuit substrate on which the control circuit is mounted, and a second circuit substrate provided opposite to the first circuit substrate, and to which the operation signal is input from the external light receiving unit. The light receiving element and the light emitting element are provided on the first circuit substrate and the second circuit substrate, respectively.

Abstract translation: 投影显示装置允许在控制电路基板上扩展用于安装电子部件的空间。 该投影显示装置包括：控制电路基板，其上安装有控制电路，用于根据来自外部光接收单元的输入操作信号控制装置中的每个装置的驱动; 以及包括发光元件和光接收元件并且设置在电路基板上的传导通道中的信号传输电路。 控制电路基板包括安装控制电路的第一电路基板和与第一电路基板相对设置的第二电路基板，并且从外部光接收单元输入操作信号。 光接收元件和发光元件分别设置在第一电路基板和第二电路基板上。

公开(公告)号：US06370767B1

公开(公告)日：2002-04-16

申请号：US09411572

申请日：1999-10-04

Applicant: Terry B. Solberg ,  Daryl E. Weispfennig ,  Michael K. Hennies

Inventor： Terry B. Solberg ,  Daryl E. Weispfennig ,  Michael K. Hennies

IPC: H05K332

CPC classification number: H05K1/0203 ,  H05K1/056 ,  H05K2201/10446 ,  H05K2201/10924 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49144 ,  Y10T29/5139

Abstract: A method and apparatus for dissipating heat from an electrical component. The method includes providing a planar element including a first electrically and thermally conductive region and a second electrically and thermally conductive region, such that the first and second regions define a spacing therebetween, and wherein the planar element includes at least one mechanically stabilizing tie connected between the first and second regions across the spacing, directly connecting a first terminal of an electrical component to the first region, directly connecting a second terminal of the electrical component to the second regions, such that the electrical component bridges the spacing, and removing the at least one mechanically stabilizing tie from between the first and second regions.

Abstract translation: 一种用于从电气部件散热的方法和装置。 该方法包括提供包括第一导电和导热区域和第二导电和导热区域的平面元件，使得第一和第二区域之间形成间隔，并且其中平面元件包括连接在 跨越间隔的第一和第二区域，直接将电气部件的第一端子连接到第一区域，将电气部件的第二端子直接连接到第二区域，使得电气部件桥接间隔，并且移除 在第一和第二区域之间的至少一个机械稳定的连接。

公开(公告)号：US06369445B1

公开(公告)日：2002-04-09

申请号：US09670107

申请日：2000-09-26

Applicant: Theodore A. Khoury

Inventor： Theodore A. Khoury

IPC: H01L2304

CPC classification number: G01R1/06716 ,  G01R1/045 ,  G01R1/07307 ,  H01L23/13 ,  H01L2224/49175 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01R13/2407 ,  H01R13/514 ,  H05K1/142 ,  H05K2201/048 ,  H05K2201/09172 ,  H05K2201/10446 ,  H05K2201/10568 ,  H05K2203/041 ,  H05K2203/049 ,  H05K2203/167 ,  H01L2924/00

Abstract: An integrated circuit (IC) having a plurality of IC modules, each IC module having attachment surfaces to which elements of the IC are attached, and each IC module having interlocking edges adjacent to the attachment surface. The interlocking edges of adjacent IC modules are interlocked to form a structural connection between the IC modules. The interlocking edges are a plurality of teeth and recesses, which are arranged in rows. The teeth are securely received by a respective recess in an adjacent interlocking edge to create a structural connection between adjacent IC modules. In addition, the interlocking edges can be a ridge member or a ridge recess, where the ridge member or ridge recess is securely received by a respective ridge recess or ridge member of an adjacent IC module to create a structural connection between the IC modules. The interconnection edge can also be a combination of the ridge member, ridge recess, and/or the rows of teeth and recesses. The attachment surfaces of adjacent IC modules can be co-planar and non-planar, depending on the shape desired. The elements on the IC modules communicate using external pathways and/or internal pathways using conventional wire-bond techniques or using conductive layers within the IC module. The IC module is formed of conventional Si wafers. Using this configuration, an IC can be constructed that utilizes less real estate, fits in non-planar spaces in a housing, and has improved speed due to reduced pathway lengths.