公开(公告)号：US20150373846A1

公开(公告)日：2015-12-24

申请号：US14764795

申请日：2014-07-30

Applicant: KYOCERA CORPORATION

Inventor： Kouichi KAWASAKI

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/111 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49838 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3431 ,  H05K3/4629 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/09663 ,  H05K2201/097 ,  H05K2201/098 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/2054 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A wiring board has an insulation base plate, and a plurality of electrodes provided adjacent to each other in plan view on the insulation base plate, the electrodes have an opening in the outer periphery and a slit oriented from the outer periphery to the interior, and, among two electrodes adjacent to each other, the slit in one electrode has a central line intersecting the outer periphery of the other electrode.

Abstract translation: 布线板具有绝缘基板和在绝缘基板上的平面图中彼此相邻设置的多个电极，电极在外周具有开口，并且具有从外周到内部的狭缝，以及 在彼此相邻的两个电极中，一个电极中的狭缝具有与另一个电极的外周相交的中心线。

公开(公告)号：US20150340149A1

公开(公告)日：2015-11-26

申请号：US14541552

申请日：2014-11-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dong Hwan LEE ,  Chan YOON ,  Hye Yeon CHA ,  Jin Woo HAN

IPC: H01F27/28 ,  H05K1/11 ,  H01F27/29 ,  H05K1/18 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F27/24 ,  H01F27/292 ,  H01F2017/0066 ,  H01F2017/0073 ,  H01F2027/2809 ,  H05K1/111 ,  H05K1/165 ,  H05K1/181 ,  H05K3/241 ,  H05K2201/0347 ,  H05K2201/086 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2201/1003 ,  H05K2201/10636 ,  H05K2203/1476 ,  Y02P70/611

Abstract: A chip electronic component may include a magnetic material body including an insulating substrate and coil conductor patterns formed on at least one surface of the insulating substrate, and external electrodes disposed on both end portions of the magnetic material body so as to be connected to end portions of the coil conductor patterns, respectively. In a cross section of the magnetic material body in a length direction, a thickness of an innermost loop/section of the coil conductor patterns may be smaller than a thickness of the remaining loops/sections of the coil conductor pattern.

Abstract translation: 芯片电子部件可以包括：磁性材料体，包括绝缘基板和形成在绝缘基板的至少一个表面上的线圈导体图案;以及外部电极，设置在磁性材料体的两端部，以便连接到端部 的线圈导体图案。 在磁性材料体的长度方向的截面中，线圈导体图案的最内圈/截面的厚度可以小于线圈导体图案的剩余环/厚度。

公开(公告)号：US09173284B2

公开(公告)日：2015-10-27

申请号：US14068029

申请日：2013-10-31

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： Kuo-Fu Su ,  Gwun-Jin Lin

IPC: H05K1/00 ,  H05K1/02 ,  H01B7/08 ,  H05K3/28

CPC classification number: H05K1/024 ,  H01B7/0838 ,  H01B7/0861 ,  H05K1/0242 ,  H05K1/025 ,  H05K3/28 ,  H05K3/281 ,  H05K2201/0323 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09881

Abstract: A planarized cover layer structure of a flexible circuit board includes an insulation layer bonded through a first adhesive layer to a surface of each one of conductive signal lines laid on a substrate of a flexible circuit board. Separation areas respectively formed between adjacent ones of the conductive signal lines are each formed with a filling layer, so that the filling layer provides the first adhesive layer with a planarization height in the separation areas and the planarization height is substantially equal to the height of the conductive signal lines. The filling layer can alternatively be of a height that is higher than the surface of the conductor layer by a covering height so that the first adhesive layer has a planarization height in the separation areas and the planarization height is substantially equal to the sum of the height of the conductive signal lines and the covering height.

Abstract translation: 柔性电路板的平面化覆盖层结构包括通过第一粘合剂层粘合到布置在柔性电路板的基板上的每个导电信号线的表面的绝缘层。 分别在相邻的导电信号线之间形成的分离区域各自形成有填充层，使得填充层在分离区域中为第一粘合剂层提供平坦化高度，并且平坦化高度基本上等于 导电信号线。 填充层可以替代地具有比导体层的表面高一个覆盖高度的高度，使得第一粘合剂层在分离区域中具有平坦化高度，并且平坦化高度基本上等于高度 的导电信号线和覆盖高度。

公开(公告)号：US20150235757A1

公开(公告)日：2015-08-20

申请号：US14184632

申请日：2014-02-19

Applicant: General Electric Company

Inventor： Alan Carroll Lovell ,  Mark Eugene Shepard ,  Andrew David McArthur ,  Qin Chen ,  Todd David Greenleaf

IPC: H01F27/28 ,  H01F41/32

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F27/24 ,  H01F27/2885 ,  H01F41/0206 ,  H01F41/043 ,  H01F41/32 ,  H01F2017/008 ,  H01F2027/2809 ,  H01F2027/2819 ,  H05K1/0224 ,  H05K1/0254 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/165 ,  H05K3/46 ,  H05K2201/0715 ,  H05K2201/09672 ,  H05K2201/098 ,  Y10T29/4902 ,  Y10T29/49073

Abstract: A device includes a printed circuit board (PCB). The device may also include a high voltage coil disposed on the PCB and a low voltage coil disposed on the PCB. Further, a conductive shield forms a three-dimensional enclosure around the high voltage coil and confines an electric field generated by the device to the PCB.

Abstract translation: 一种设备包括印刷电路板（PCB）。 该装置还可以包括布置在PCB上的高压线圈和布置在PCB上的低压线圈。 此外，导电屏蔽件围绕高压线圈形成三维外壳，并将该器件产生的电场限制在PCB上。

公开(公告)号：US20150228416A1

公开(公告)日：2015-08-13

申请号：US14555633

申请日：2014-11-27

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H01G17/00 ,  H05K1/18 ,  H05K1/11 ,  H03H7/01 ,  H01G4/008 ,  H05K1/02 ,  H01F27/28 ,  H05K1/16 ,  H01G4/12

CPC classification number: H01G17/00 ,  H01F27/2804 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/224 ,  H01G4/228 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/97 ,  H01L28/65 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/19105 ,  H03H7/0115 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/186 ,  H05K3/005 ,  H05K3/0052 ,  H05K3/4647 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/308

Abstract: A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

Abstract translation: 由有机矩阵框架限定的芯片插座，其中所述有机矩阵框架包括至少一个通孔支柱层，其中穿过所述插座周围的框架的至​​少一个通孔包括至少一个电容器，所述电容器包括下电极，介电层和上电极 与通孔接触。

公开(公告)号：US20150201499A1

公开(公告)日：2015-07-16

申请号：US14153071

申请日：2014-01-12

Applicant: Zohar SHINAR ,  Joel VIDAL

Inventor： Zohar SHINAR ,  Joel VIDAL

IPC: H05K3/12 ,  B29C67/00

CPC classification number: H05K3/125 ,  B29C64/112 ,  B29C64/135 ,  B29C64/386 ,  B29C70/882 ,  B29K2105/0058 ,  B29K2995/0005 ,  B29K2995/0006 ,  B29K2995/0007 ,  B29L2031/3406 ,  B29L2031/3425 ,  B33Y30/00 ,  B33Y50/02 ,  B33Y80/00 ,  H05K1/0206 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/0274 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0284 ,  H05K1/092 ,  H05K1/165 ,  H05K1/167 ,  H05K1/186 ,  H05K3/0005 ,  H05K3/1283 ,  H05K3/225 ,  H05K3/284 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4664 ,  H05K3/4685 ,  H05K3/4688 ,  H05K2201/0367 ,  H05K2201/037 ,  H05K2201/0391 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/098 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/09872 ,  H05K2201/10098 ,  H05K2203/013 ,  H05K2203/107 ,  H05K2203/163 ,  H05K2203/166

Abstract: Device, system, and method of three-dimensional printing. A device includes: a first 3D-printing head to selectively discharge conductive 3D-printing material; a second 3D-printing head to selectively discharge insulating 3D-printing material; and a processor to control operations of the first and second 3D-printing heads based on a computer-aided design (CAD) scheme describing a printed circuit board (PCB) intended for 3D-printing. A 3D-printer device utilizes 3D-printing methods, in order to 3D-print: (a) a functional multi-layer PCB; or (b) a functional stand-alone electric component; or (c) a functional PCB having an embedded or integrated electric component, both of them 3D-printed in a unified 3D-printing process.

Abstract translation: 三维打印的设备，系统和方法。 一种装置包括：第一3D打印头，用于选择性地排放导电3D打印材料; 第二3D打印头，用于选择性地放电绝缘3D打印材料; 以及基于描述用于3D打印的印刷电路板（PCB）的计算机辅助设计（CAD）方案来控制第一和第二3D打印头的操作的处理器。 3D打印机设备利用3D打印方法，以便3D打印：（a）功能性多层PCB; 或（b）功能独立电气部件; 或（c）具有嵌入或集成电气部件的功能PCB，它们都以统一的3D打印过程3D打印。

公开(公告)号：US08952408B2

公开(公告)日：2015-02-10

申请号：US13710648

申请日：2012-12-11

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Tatsuaki Denda ,  Kazutaka Kobayashi

IPC: H01L33/00 ,  H01L33/60 ,  H05K1/02 ,  H01L21/50 ,  H05K1/11

CPC classification number: H01L33/60 ,  H01L21/50 ,  H01L2224/16245 ,  H01L2924/181 ,  H05K1/0203 ,  H05K1/0265 ,  H05K1/0274 ,  H05K1/111 ,  H05K2201/09409 ,  H05K2201/098 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2924/00012

Abstract: A light-emitting element mounting package includes a light-emitting element mounting portion that includes a plurality of wiring portions arranged interposing a predetermined gap between the wiring portions facing each other, and an insulating layer on which the light-emitting element mounting portion is mounted, wherein an upper surface of the light-emitting element mounting portion is exposed on the insulating layer, wherein cutout portions are formed on lower sides of side edges of the wiring portions and contact the insulating layer.

Abstract translation: 发光元件安装封装包括发光元件安装部分，该发光元件安装部分包括布置在彼此面对的布线部之间的预定间隙的多个布线部分和安装有发光元件安装部分的绝缘层 其中，所述发光元件安装部的上表面露出在所述绝缘层上，在所述布线部的侧缘的下侧形成有切口部，并与所述绝缘层接触。

公开(公告)号：US20150027751A1

公开(公告)日：2015-01-29

申请号：US14068029

申请日：2013-10-31

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： KUO-FU SU ,  GWUN-JIN LIN

IPC: H05K1/02

CPC classification number: H05K1/024 ,  H01B7/0838 ,  H01B7/0861 ,  H05K1/0242 ,  H05K1/025 ,  H05K3/28 ,  H05K3/281 ,  H05K2201/0323 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09881

Abstract: A planarized cover layer structure of a flexible circuit board includes an insulation layer bonded through a first adhesive layer to a surface of each one of conductive signal lines laid on a substrate of a flexible circuit board. Separation areas respectively formed between adjacent ones of the conductive signal lines are each formed with a filling layer, so that the filling layer provides the first adhesive layer with a planarization height in the separation areas and the planarization height is substantially equal to the height of the conductive signal lines. The filling layer can alternatively be of a height that is higher than the surface of the conductor layer by a covering height so that the first adhesive layer has a planarization height in the separation areas and the planarization height is substantially equal to the sum of the height of the conductive signal lines and the covering height.

Abstract translation: 柔性电路板的平面化覆盖层结构包括通过第一粘合剂层粘合到布置在柔性电路板的基板上的每个导电信号线的表面的绝缘层。 分别在相邻的导电信号线之间形成的分离区域各自形成有填充层，使得填充层在分离区域中为第一粘合剂层提供平坦化高度，并且平坦化高度基本上等于 导电信号线。 填充层可以替代地具有比导体层的表面高一个覆盖高度的高度，使得第一粘合剂层在分离区域中具有平坦化高度，并且平坦化高度基本上等于高度 的导电信号线和覆盖高度。

公开(公告)号：US20140347836A1

公开(公告)日：2014-11-27

申请号：US14455052

申请日：2014-08-08

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Youko NAKAMURA ,  Norihiro NASHIDA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0296 ,  H01L21/56 ,  H01L21/563 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/01 ,  H01L25/072 ,  H01L31/048 ,  H01L33/52 ,  H01L33/56 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/115 ,  H05K1/185 ,  H05K2201/09609 ,  H05K2201/09727 ,  H05K2201/098 ,  H01L2924/00

Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.

Abstract translation: 半导体器件包括：导电图案化绝缘基板; 导电块固定到导电图案化的绝缘衬底的导电图案上; 固定到每个导电块的半导体芯片; 印刷电路板，其具有固定到所述半导体芯片的导电柱; 和树脂。 半导体器件被配置为使得相应的导电块固定到其周围的每个导电图案的每单位面积的导电膜的平均体积从导电块朝向外部减小。

公开(公告)号：US20140054069A1

公开(公告)日：2014-02-27

申请号：US13997544

申请日：2011-12-23

Applicant: Sang Myung Lee ,  Sung Woon Yoon ,  Hyuk Soo Lee ,  Sung Won Lee ,  Ki Do Chun

Inventor： Sang Myung Lee ,  Sung Woon Yoon ,  Hyuk Soo Lee ,  Sung Won Lee ,  Ki Do Chun

IPC: H05K1/02 ,  H05K3/20

CPC classification number: H05K1/0298 ,  H05K3/202 ,  H05K3/4647 ,  H05K3/465 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/098 ,  H05K2203/0323 ,  H05K2203/0376

Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Abstract translation: 公开了一种印刷电路板及其制造方法。 印刷电路板包括芯绝缘层，至少一个通过芯绝缘层形成的通孔，埋在芯绝缘层中的内电路层，以及在芯绝缘层的顶表面或底表面上的外电路层 其中所述通孔包括具有第一宽度的中心部分和具有第二宽度的接触部分，所述接触部分与所述芯绝缘层的表面接触，并且所述第一宽度大于所述第二宽度。 同时形成内部电路层和通孔，从而减少工艺步骤。 由于设置了奇数电路层，所以印刷电路板具有轻薄的结构。