公开(公告)号：US20170288349A1

公开(公告)日：2017-10-05

申请号：US15433399

申请日：2017-02-15

Applicant: CommScope Technologies LLC

Inventor： Bernard Harold Hammond, JR. ,  David Patrick Murray ,  Ian Robert George

IPC: H01R13/719

CPC classification number: H01R13/6466 ,  H01R4/2416 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/64 ,  H01R2107/00 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49117 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.

公开(公告)号：US20170162987A1

公开(公告)日：2017-06-08

申请号：US14962131

申请日：2015-12-08

Applicant: INTEL CORPORATION

Inventor： Vijay KASTURI

IPC: H01R24/50 ,  H05K1/02

CPC classification number: H01R24/50 ,  H01R12/526 ,  H01R12/53 ,  H05K1/0219 ,  H05K1/0298 ,  H05K1/117 ,  H05K1/14 ,  H05K3/32 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: An adaptor board may include a multi-layer circuit board having at least three layers, namely a first board layer, a second board layer, and a third board layer. A first plurality of cable contacts may be provided at the first board layer, and a second plurality of cable contacts may be provided at the third board layer.

公开(公告)号：US09613903B2

公开(公告)日：2017-04-04

申请号：US14954200

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ying Lee ,  Jyu-Horng Shieh

IPC: H01L21/306 ,  H01L23/522 ,  H01L23/528 ,  H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L2924/0002 ,  H05K1/0296 ,  H05K1/11 ,  H05K3/002 ,  H05K2201/09236 ,  H01L2924/00

Abstract: A hard mask is disposed over a base material, and an I-shaped first opening is disposed in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.

公开(公告)号：US09537197B2

公开(公告)日：2017-01-03

申请号：US14559503

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Darryl Jessie ,  Lan Nan

IPC: H01P3/00 ,  H01L23/00 ,  H01L23/66 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01P3/006 ,  H01L21/768 ,  H01L23/5225 ,  H01L23/525 ,  H01L23/528 ,  H01L23/66 ,  H01L24/11 ,  H01L24/14 ,  H01L2223/6605 ,  H01L2223/6627 ,  H01P3/003 ,  H05K1/0219 ,  H05K2201/0305 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09618

Abstract: In an integrated circuit package that houses radio-frequency (RF) circuits or components using wafer-level packaging (WLP), an RF-signal transmission structure includes a signal-carrying conductive line positioned between grounded conductive lines to avoid undesirable coupling between the signal-carrying conductive line and other RF circuits or components in the same package.

Abstract translation: 在使用晶片级封装（WLP）容纳射频（RF）电路或部件的集成电路封装中，RF信号传输结构包括位于接地导线之间的信号承载导线，以避免信号之间的不期望的耦合 - 同一封装中的导线和其他RF电路或组件。

公开(公告)号：US09530457B2

公开(公告)日：2016-12-27

申请号：US14519967

申请日：2014-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US20160268666A1

公开(公告)日：2016-09-15

申请号：US15159967

申请日：2016-05-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuki WAKABAYASHI ,  Bunta OKAMOTO ,  Satoshi SASAKI

IPC: H01P3/08 ,  H05K1/02

CPC classification number: H01P3/08 ,  H01P1/2039 ,  H01P3/082 ,  H05K1/0237 ,  H05K1/028 ,  H05K1/111 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: A high-frequency signal line includes a dielectric base with a first line portion and a second line portion each extending along a predetermined straight line parallel or substantially parallel to a predetermined direction, and a third line portion mutually connecting first side ends of the first line portion and the second line portion in the predetermined direction, a signal line, a first ground conductor located on the first side in the layer stacking direction of the signal line, a second ground conductor located on a second side in the layer stacking direction of the signal line, and one or more interlayer connection conductors connecting the first ground conductor and the second ground conductor. In the third line portion, the interlayer connection conductor is provided on the second side in the predetermined direction of the signal line when viewed from the layer stacking direction.

Abstract translation: 高频信号线包括：电介质基底，具有第一线部分和第二线部分，每个第二线部分沿着与预定方向平行或基本平行的预定直线延伸;以及第三线部分，其相互连接第一线的第一侧端 部分和第二线部分，信号线，位于信号线的层叠方向的第一侧的第一接地导体，位于第二接线导体的层叠方向上的第二接地导体 信号线和连接第一接地导体和第二接地导体的一个或多个层间连接导体。 在第三行部分中，当从层叠方向观察时，层间连接导体设置在信号线的预定方向上的第二侧上。

公开(公告)号：US20160148911A1

公开(公告)日：2016-05-26

申请号：US14903858

申请日：2014-07-08

Applicant: PSI CO., LTD.

Inventor： Young Rag Do

IPC: H01L25/075 ,  H01L33/38 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L33/38 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0066 ,  H05K1/0295 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2201/10583 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2203/048 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be aligned and connected to two electrodes different from each other to solve a limitation in which a nano-scale LED device having a nano unit is coupled to two electrodes different from each other in a stand-up state. Also, since the LED device and the electrodes are disposed on the same plane, light extraction efficiency of the LED device may be improved. Furthermore, the number of nano-scale LED devices may be adjusted. Second, since the nano-scale LED device does not stand up to be three-dimensionally coupled to upper and lower electrodes, but lies to be coupled to two electrodes different from each other on the same plane, the light extraction efficiency may be very improved. Also, since a separate layer is formed on a surface of the LED device to prevent the LED device and the electrode from being electrically short-circuited, defects of the LED electrode assembly may be minimized. Also, in preparation for the occurrence of the very rare defects of the LED device, the plurality of LED devices may be connected to the electrode to maintain the original function of the nano-scale LED electrode assembly.

Abstract translation: 提供了一种纳米级LED组件及其制造方法。 首先，独立制造的纳米级LED器件可以对准并连接到彼此不同的两个电极，以解决将具有纳米单元的纳米级LED器件耦合到彼此不同的两个电极的限制 站立状态。 此外，由于LED器件和电极设置在同一平面上，所以可以提高LED器件的光提取效率。 此外，可以调整纳米级LED器件的数量。 第二，由于纳米尺度的LED器件不能立即连接到上电极和下电极，而是要被连接到在同一平面上彼此不同的两个电极，所以光提取效率可以非常改善 。 此外，由于在LED器件的表面上形成单独的层以防止LED器件和电极电短路，所以可以使LED电极组件的缺陷最小化。 此外，为了准备LED装置的非常罕见的缺陷的发生，可以将多个LED器件连接到电极以保持纳米级LED电极组件的原始功能。

公开(公告)号：US20160133357A1

公开(公告)日：2016-05-12

申请号：US14538102

申请日：2014-11-11

Applicant: Ronald Steven Cok ,  James Edward Sutton

Inventor： Ronald Steven Cok ,  James Edward Sutton

IPC: H01B13/00 ,  C23C18/16

CPC classification number: C23C18/1633 ,  C09D11/52 ,  C23C18/1608 ,  C23C18/208 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0274 ,  H05K3/185 ,  H05K2201/0108 ,  H05K2201/09236

Abstract: Electrically-conductive articles are prepared to have electrically-conductive metallic grids and electrically-conductive metallic connectors (BUS lines) on one or both supporting sides of a transparent substrate. The electrically-conductive metallic connectors are designed with one metallic main wire that comprises two or more adjacent metallic micro-wires in bundled patterns. These bundled patterns and metallic micro-wires are designed with specific dimensions and configurations to provide optimal fidelity (or correspondence) to the mask image used to provide such patterns. The electrically-conductive articles can be prepared using various manufacturing technologies and can be used as parts of various electronic devices including touch screen devices. The electrically-conductive metallic grids and connectors can be prepared and designed using various technologies that are amenable to obtaining very fine lines in predetermined patterns.

Abstract translation: 制备导电制品以在透明基底的一个或两个支撑侧上具有导电金属网格和导电金属连接器（BUS线）。 导电金属连接器设计有一个金属主导线，其包括两个或更多个相邻的金属微线束的捆绑图案。 这些捆绑图案和金属微线设计具有特定的尺寸和配置，以提供用于提供这种图案的掩模图像的最佳保真度（或对应关系）。 导电制品可以使用各种制造技术制备，并且可以用作包括触摸屏装置的各种电子装置的部件。 导电金属网格和连接器可以使用各种可以以预定图案获得非常细的线条的技术来制备和设计。

公开(公告)号：US09265140B2

公开(公告)日：2016-02-16

申请号：US13910213

申请日：2013-06-05

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young-Tak Han ,  Jang Uk Shin ,  Sang Ho Park ,  Yongsoon Baek

IPC: H05K7/00 ,  H05K1/18 ,  H05K1/02 ,  H05K1/14 ,  H05K1/00 ,  H05K5/00

CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0221 ,  H05K1/141 ,  H05K1/142 ,  H05K1/144 ,  H05K1/145 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/10121

Abstract: Provided are structures for connecting trace lines of printed circuit boards and optical transceiver modules with the same. The module may include an optical transmitter/receiver part, a signal processing unit, a flexible PCB, and a rigid PCB. The flexible PCB may include a first signal line, and the rigid PCB may include a second signal line. The flexible PCB and the rigid PCB may be overlapped with each other. The first signal line and the second signal line may not be overlapped with each other and be electrically connected to each other by a junction soldering structure. It is possible to transmit high quality and high frequency signals through the first and second signal lines.

Abstract translation: 提供了用于连接印刷电路板的轨迹线和具有该印刷电路板的光收发器模块的结构。 该模块可以包括光发射器/接收器部分，信号处理单元，柔性PCB和刚性PCB。 柔性PCB可以包括第一信号线，并且刚性PCB可以包括第二信号线。 柔性PCB和刚性PCB可以彼此重叠。 第一信号线和第二信号线可以彼此不重叠并且通过连接焊接结构彼此电连接。 可以通过第一和第二信号线传输高质量和高频信号。

公开(公告)号：US20150370954A1

公开(公告)日：2015-12-24

申请号：US14309060

申请日：2014-06-19

Applicant: Cisco Technology, Inc.

Inventor： Lin Shen ,  Yongming Xiong ,  Stephen Ong ,  Shahbaz Mahmood

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H01L2924/0002 ,  H01P3/081 ,  H04L25/027 ,  H05K1/0216 ,  H05K1/0245 ,  H05K2201/09236

Abstract: A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees.

Abstract translation: 一种用于匹配差分信号对的迹线长度的方法和装置。 该方法包括确定第一迹线比第二迹线长，并且修改第二迹线使得该长度基本上等于第一迹线的长度。 在一些实现中，可以通过用长度基本上相等并且在小于180度的顶点处相交的两个线段替换轨迹的一个或多个部分来修改第二轨迹。