公开(公告)号：US07721238B2

公开(公告)日：2010-05-18

申请号：US11231642

申请日：2005-09-21

Applicant: Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

Inventor： Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

Abstract translation: 一种用于输入设计有印刷电路板（PCB）可安装部件的多个不同电路原理图的方法和装置; 提取用于所述多个不同电路原理图的电路拓扑; 将所述提取的电路拓扑转换为固定数量的连接点; 以及生成具有所述固定数量的连接点的可配置电路PCB物理布局图案，使得当位于所述固定数量的连接点中的一个或多个连接点上时所述PCB可安装部件可以实现由所述多个不同电路原理图表示的任何电路。

公开(公告)号：US20090199149A1

公开(公告)日：2009-08-06

申请号：US12027146

申请日：2008-02-06

Applicant: David Kwong

Inventor： David Kwong

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5077 ,  H05K1/116 ,  H05K3/0005 ,  H05K3/429 ,  H05K2201/094 ,  H05K2201/09454

Abstract: Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are proviuded on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second radius R2 if the via is not connected to any trace on the corresponding intermediate layer. If a trace is connected to a dynamic via, the via radius changes from the second radius R2 to a first radius R1, where R1 is greater than R2.

Abstract translation: 提供了用于设计和布置多层电路基板（例如多层PCB）的方法和装置。 动态通孔在中间PCB层上提供。 每个动态通道具有根据相应中间层的跟踪布局进行调整的功能。 特别地，如果通孔没有连接到相应中间层上的任何迹线，则每个动态通孔具有第二半径R2。 如果迹线连接到动态通孔，则通孔半径从第二个半径R2变为第一个半径R1，其中R1大于R2。

公开(公告)号：US07544304B2

公开(公告)日：2009-06-09

申请号：US11484531

申请日：2006-07-11

Applicant: Hisashi Matsumoto ,  Mark Singer ,  Leo Baldwin ,  Jeffrey E. Howerton ,  David V. Childers

Inventor： Hisashi Matsumoto ,  Mark Singer ,  Leo Baldwin ,  Jeffrey E. Howerton ,  David V. Childers

IPC: H01B13/00

CPC classification number: H05K3/0035 ,  B23K26/03 ,  B23K26/06 ,  B23K26/389 ,  B23K2101/42 ,  H05K1/0269 ,  H05K2201/09454 ,  H05K2203/163

Abstract: A process for laser forming a blind via in at least one layer of a circuit substrate having a plurality of capture pads of varying geometry can include, for at least one blind via to be formed in at least one layer of a circuit substrate, evaluating a capture pad geometry value (such as area and/or volume) within a predetermined distance from a drilling location with respect to a blind via geometry value (such as area and/or volume) to be formed at the drilling location. The process can include setting at least one laser operating parameter based on the evaluation in order to obtain a desired capture pad appearance after blind via formation. The process can include imaging a capture pad area defined as an area within a predetermined distance from a blind via drilling location in at least one layer of a circuit substrate, quantifying at least one appearance value for the imaged capture pad area, and determining an acceptability of the imaged capture pad areas based on the quantified appearance value.

Abstract translation: 用于在具有多个不同几何形状的多个捕获垫的电路基板的至少一层中激光形成盲通孔的方法可以包括：至少一个盲孔以形成在电路基板的至少一层中， 相对于在钻孔位置处形成的盲孔通孔几何值（例如面积和/或体积），距离钻孔位置预定距离内的捕获垫几何值（例如面积和/或体积）。 该过程可以包括基于评估设置至少一个激光操作参数，以便在盲通孔形成之后获得期望的捕获垫外观。 该过程可以包括将被定义为距电路基板的至少一层中的盲孔通孔位置的预定距离范围内的捕获区域成像，量化成像捕获区域的至少一个出现值，以及确定可接受性 基于量化外观值的成像捕获垫区域。

公开(公告)号：US20090133919A1

公开(公告)日：2009-05-28

申请号：US12198794

申请日：2008-08-26

Applicant: Kenji Hasegawa

Inventor： Kenji Hasegawa

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/421 ,  H05K1/0265 ,  H05K1/116 ,  H05K3/429 ,  H05K3/465 ,  H05K2201/09036 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09736 ,  Y10T29/49155

Abstract: A multilayer printed wiring board includes: an insulating base including an indentation section formed thereon; a conductor pattern formed on the insulating base, the conductor pattern including a thick film section formed by embedding a conductor in the indentation section; and a via hole section formed in an upper layer of the insulating base, the via hole section including a bottom portion that is in contact with the thick film section.

Abstract translation: 多层印刷线路板包括：绝缘基底，包括形成在其上的凹陷部分; 形成在所述绝缘基底上的导体图案，所述导体图案包括通过将导体嵌入所述凹部而形成的厚膜部; 以及形成在所述绝缘基底的上层中的通孔部，所述通孔部包括与所述厚膜部接触的底部。

公开(公告)号：US20080257596A1

公开(公告)日：2008-10-23

申请号：US12102303

申请日：2008-04-14

Applicant: Kentaro Kaneko

Inventor： Kentaro Kaneko

IPC: H05K1/11 ,  H05K3/46 ,  H01L21/60

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/382 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/098 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and a first electrode pad 130 is formed on a chip mounting side. A taper surface 132 of the first electrode pad 130 has a gradient in an orientation reduced in an upward direction toward a solder connecting side or a chip mounting side. Therefore, a holding force for a force applied to the solder connecting side or the chip mounting side is increased, and furthermore, the taper surface 132 adheres to a tapered internal wall of an insulating layer of a first layer so that a bonding strength to the insulating layer is increased.

Abstract translation: 半导体器件100具有半导体芯片110倒装芯片安装在布线板120上的结构。布线板120具有布置多个布线层和多​​个绝缘层的多层结构，并且 第一电极焊盘130形成在芯片安装侧。 第一电极焊盘130的锥形表面132具有沿向上朝向焊接连接侧或芯片安装侧减小的取向的梯度。 因此，施加到焊料连接侧或芯片安装侧的力的保持力增大，此外，锥形表面132粘附到第一层的绝缘层的锥形内壁，使得与 绝缘层增加。

公开(公告)号：US07312523B2

公开(公告)日：2007-12-25

申请号：US11161285

申请日：2005-07-28

Applicant: Jean J. Audet ,  Jon A. Casey ,  Luc Guerin ,  David L. Questad ,  David J. Russell

Inventor： Jean J. Audet ,  Jon A. Casey ,  Luc Guerin ,  David L. Questad ,  David J. Russell

IPC: H01L23/053 ,  H01L23/12 ,  H01L23/48

CPC classification number: H05K1/116 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2924/00

Abstract: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 μm. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 μm. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

Abstract translation: 电路板包括填充树脂的电镀（RFP）通孔; 在RFP通孔上的电介质层; 电介质层中的大致圆形的RFP帽，并连接到RFP通孔的上部开口; 电介质层中的通孔叠层; 以及从所述通孔叠层径向向外延伸的多个通孔焊盘，其中所述多个通路焊盘中的每一个在径向上大于所述RFP盖。 优选地，RFP帽包括至少300μm的直径。 优选地，每个通孔焊盘包括具有至少400μm直径的基本圆形形状。 此外，电路板还包括连接到通孔叠层的球栅阵列垫; 以及连接到球栅阵列垫的输入/输出球栅阵列垫。 此外，电路板还包括电介质层中的金属平面。

公开(公告)号：US20070039171A1

公开(公告)日：2007-02-22

申请号：US11537754

申请日：2006-10-02

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H01R43/00

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: Method and apparatus are disclosed for flow control over Point-to-Point Protocol (PPP) data links. A method of negotiating such flow control between two PPP peers is disclosed, along with methods for operating flow control across a PPP link. In one embodiment, flow control frames carry an IEEE802.3x MAC control frame payload—the PPP implementation repackages such frames as MAC control frames and passes them to a MAC, which performs flow control. In another embodiment, flow control frames allow flow control commands to be applied differently to different service classes such that PPP flow can be controlled on a per-class basis.

Abstract translation: 公开了用于在点对点协议（PPP）数据链路上的流控制的方法和装置。 公开了一种在两个PPP对等体之间协商这种流量控制的方法，以及用于在PPP链路上操作流量控制的方法。 在一个实施例中，流控制帧携带IEEE802.3x MAC控制帧有效载荷 - PPP实现将诸如MAC控制帧的帧重新封装，并将其传递给执行流控制的MAC。 在另一个实施例中，流控制帧允许流控制命令被不同地应用于不同的服务类，使得PPP流可以基于每个级别进行控制。

公开(公告)号：US20070028202A1

公开(公告)日：2007-02-01

申请号：US11251770

申请日：2005-10-18

Applicant: Taketsugu Kawamichi ,  Hiroshi Nakamura ,  Eiichi Konno

Inventor： Taketsugu Kawamichi ,  Hiroshi Nakamura ,  Eiichi Konno

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H05K1/116 ,  H05K3/0005 ,  H05K2201/09454 ,  H05K2201/09536

Abstract: An apparatus generates design information on a via hole that passes through predetermined layers of a multilayer wiring board. A storing unit stores information on at least one of a shape and a size of a land to be provided around the via hole. A design-information generating unit generates the design information, when designing a via hole that passes through a plurality of internal layers of the wiring board, by applying the information on one kind of land for an internal layer to each of the internal layers through which the via hole passes.

Abstract translation: 一种设备在通过多层布线板的预定层的通孔上产生设计信息。 存储单元存储关于要设置在通孔周围的区域的形状和尺寸中的至少一个的信息。 设计信息生成单元在设计通过布线板的多个内部层的通孔时，通过将内部层的一种用于上述的内部层的信息应用于内部的各层，生成设计信息 通孔通过。

公开(公告)号：US07152312B2

公开(公告)日：2006-12-26

申请号：US10073701

申请日：2002-02-11

Applicant: Gary Gottlieb

Inventor： Gary Gottlieb

IPC: H01R43/00 ,  H05K3/36

CPC classification number: H05K1/116 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for transmitting high-frequency current through a substrate is provided. The method comprises receiving the high-frequency current at a via passing through at least one conductive plane disposed within the substrate and coupled to the via with one or more tabs which span a gap between the at least one conductive plane and the via; and directing the high-frequency current along an uninterrupted path substantially on a surface of the via thereby bypassing the at least one conductive plane by conducting at least a portion of the high-frequency current between the one or more tabs.

Abstract translation: 提供了一种通过基板传输高频电流的方法。 该方法包括在穿过设置在衬底内的至少一个导电平面的通孔处接收高频电流，并且通过跨越至少一个导电平面和通孔之间的间隙的一个或多个接片连接到通孔; 以及基本上在所述通孔的表面上沿着不间断的路径引导所述高频电流，从而通过在所述一个或多个突片之间传导所述高频电流的至少一部分来绕过所述至少一个导电平面。

公开(公告)号：US20060183316A1

公开(公告)日：2006-08-17

申请号：US11397713

申请日：2006-04-05

Applicant: James Larnerd ,  John Lauffer ,  Voya Markovich ,  Kostas Papathomas

Inventor： James Larnerd ,  John Lauffer ,  Voya Markovich ,  Kostas Papathomas

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

Abstract translation: 一种制造印刷电路板的方法，其中导电通孔形成在板结构的两个电介质层内，以便连接指定的导电层。 一个孔连接两个相邻的层，另一个连接两个相邻的层，包括通过另一个孔连接的一个导电层。 也可以使用一个或多个孔连接所有三个导电层。 所得到的孔可以例如用金属电镀或导电或不导电的糊料填充。 在后者的情况下，也可以在浆料上方设置顶部覆盖导电层，例如在板的外表面上用作衬垫等。