公开(公告)号：US09900982B2

公开(公告)日：2018-02-20

申请号：US14539545

申请日：2014-11-12

Applicant: Finisar Corporation

Inventor： Henry Nguyen ,  Yuxin Zhou ,  Tay Gek-Teng

IPC: H05K7/10 ,  H05K1/11 ,  H05K1/02 ,  H05K3/36 ,  H05K3/40

CPC classification number: H05K1/113 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K1/111 ,  H05K3/363 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/0373 ,  H05K2201/09381 ,  H05K2201/09445 ,  H05K2201/09845 ,  H05K2203/0465 ,  Y02P70/611 ,  H01L2924/00

Abstract: A method of soldering can include: providing a first electronic component having a first buttoned soldering pad including a first soldering pad and one or more first button heads protruding from a first surface of the soldering pad; providing a second electronic component having a soldering pad; and soldering the first buttoned soldering pad to the soldering pad. The method includes introducing solder to spaces around the one or more first buttons of the first buttoned soldering pad. The method includes introducing a first solder to spaces around the one or more first buttons of the first buttoned soldering pad; introducing a second solder to spaces around one or more second buttons of a second buttoned soldering pad of the first electronic component; and forming spaces between the first and second solder that electronically insulate the first solder from the second solder.

公开(公告)号：US09883593B2

公开(公告)日：2018-01-30

申请号：US14714531

申请日：2015-05-18

Applicant: KyongSoon Cho ,  Yungcheol Kong

Inventor： KyongSoon Cho ,  Yungcheol Kong

IPC: H05K1/00 ,  H05K1/18 ,  H01L25/16 ,  H01L25/065 ,  H01L25/10 ,  H05K1/02 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H05K3/46

CPC classification number: H05K1/189 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/028 ,  H05K1/181 ,  H05K3/4697 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2224/83 ,  H01L2224/81

Abstract: Provided are semiconductor modules and semiconductor packages. The semiconductor module may include a module substrate and a semiconductor package mounted on the module substrate. The semiconductor package may include a substrate with a top surface and a bottom surface. Here, the top surface of the substrate may be flat and the bottom surface of the substrate may include a first region and a second region positioned at a lower level than the first region. The semiconductor package may further include connecting portions which are provided on the bottom surface of the substrate and electrically connected to the module substrate.

公开(公告)号：US09877387B2

公开(公告)日：2018-01-23

申请号：US14779232

申请日：2014-03-26

Applicant: KYOCERA Corporation

Inventor： Satoshi Kajita ,  Mitsuhiro Hagihara ,  Yuuhei Matsumoto

IPC: H05K7/00 ,  H05K1/03 ,  H05K1/11 ,  H05K3/42 ,  H05K1/02 ,  H05K1/09 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0038 ,  H05K3/421 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072

Abstract: A wiring board includes: an inorganic insulating layer having a via hole formed so as to penetrate the inorganic insulating layer in a thickness direction thereof; a conductive layer disposed on the inorganic insulating layer; and a via conductor which adheres to an inner wall of the via hole and is connected with the conductive layer. The inorganic insulating layer includes a first section including a plurality of inorganic insulating particles partly connected to each other, and a resin portion located in gaps between the inorganic insulating particles, and a second section which is interposed between the first section and the via conductor, including a plurality of inorganic insulating particles partly connected to each other, and a conducting portion composed of part of the via conductor which is located in gaps between the inorganic insulating particles.

公开(公告)号：US20170374746A1

公开(公告)日：2017-12-28

申请号：US15676472

申请日：2017-08-14

Applicant: PI-CRYSTAL INCORPORATION

Inventor： Junichi TAKEYA ,  Seiichiro YAMAGUCHI ,  Masataka ITOH

IPC: H05K3/36 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K1/14

CPC classification number: H05K3/361 ,  H05K1/115 ,  H05K1/116 ,  H05K1/118 ,  H05K1/144 ,  H05K3/363 ,  H05K3/403 ,  H05K3/4038 ,  H05K3/4623 ,  H05K2201/041 ,  H05K2201/09181 ,  H05K2201/09845 ,  H05K2201/10121 ,  H05K2201/10151

Abstract: Research on practical realization of various types of printable devices has progressed, and the realization of devices in which these printable devices are integrated on a flexible board is expected. However, there is the problem that, if a plurality of printable devices are simply integrated on the same board, the area of the integrated device increases, and the yield ratio greatly decreases. An integration technique that solves the problem of an increase in the area and a decrease in the yield ratio is in demand. Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through-vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.

公开(公告)号：US20170365653A1

公开(公告)日：2017-12-21

申请号：US15362082

申请日：2016-11-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byoungyong Kim ,  Seunghwa Ha ,  Seungsoo Ryu ,  Sanghyeon Song ,  Jeongdo Yang ,  Jungyun Jo ,  Jeongho Hwang

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52

CPC classification number: H01L27/3276 ,  G02F1/13458 ,  H01L51/5253 ,  H01L51/56 ,  H05K1/111 ,  H05K1/112 ,  H05K3/32 ,  H05K3/328 ,  H05K2201/0373 ,  H05K2201/09845 ,  H05K2203/0285 ,  Y02P70/611

Abstract: A display apparatus includes a display panel comprising a display substrate on which a plurality of pad terminals is disposed, and a driving unit comprising a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.

公开(公告)号：US09848496B2

公开(公告)日：2017-12-19

申请号：US14978709

申请日：2015-12-22

Applicant: SAE MAGNETICS (H.K.) LTD.

Inventor： Akio Nakao

IPC: H05K1/14 ,  H05K3/28 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K3/284 ,  H01L21/561 ,  H01L21/568 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/15159 ,  H01L2924/15313 ,  H05K1/0218 ,  H05K3/0097 ,  H05K2201/0317 ,  H05K2201/0715 ,  H05K2201/09145 ,  H05K2201/09845

Abstract: An electronic component module includes a substrate; at least one electronic component mounted on an electronic component mounting surface of the substrate; an insulating body covering the electronic component on the electronic component mounting surface of the substrate; and a metal film formed by sputtering, the metal film covering at least one exterior surface of the insulating body and at least one side surface of the substrate. The substrate has a recess portion formed on a periphery of the surface of the substrate that is opposite to the electronic component mounting surface, and the recess portion has a top surface parallel to the electronic component mounting surface and a side surface perpendicular to the top surface, and the metal film is extended to cover the top surface of the recess portion, without covering the side surface thereof. It obtains improved electromagnetic wave shielding effect and improved manufacturing efficiency.

公开(公告)号：US09837739B2

公开(公告)日：2017-12-05

申请号：US15179372

申请日：2016-06-10

Applicant: LG ELECTRONICS INC.

Inventor： Seunghak Ryu

IPC: H01R12/77 ,  H01R13/62

CPC classification number: H01R12/774 ,  H01R12/81 ,  H01R13/6205 ,  H05K1/0298 ,  H05K1/118 ,  H05K3/361 ,  H05K2201/058 ,  H05K2201/09845

Abstract: A display device includes a display unit including a display panel providing an image, a housing spaced apart from the display unit, the housing including a main board to transmit signals to the display panel, a power supply to provide the display panel with electric power; and a cable to electrically connect with the housing and the display unit, the cable including a flat cable disposed in at least part of the cable, where the flat cable includes a plurality of layers, at least one of the plurality of layers includes a signal terminal through which the signals are transferred, and at least another one of the plurality of layers includes a power terminal through which the electric power is supplied.

公开(公告)号：US09775231B2

公开(公告)日：2017-09-26

申请号：US14947091

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Marc B. Cartier, Jr.

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11 ,  H01R43/20

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

公开(公告)号：US20170265308A1

公开(公告)日：2017-09-14

申请号：US15064440

申请日：2016-03-08

Applicant: uBeam Inc.

Inventor： Nicholas Lavada Nemeth ,  Adam Stephen Elhadad ,  Andrew Joyce ,  Sean Taffler

IPC: H05K3/00 ,  H05K3/40 ,  B23K26/38 ,  B23K26/402 ,  B23K26/06 ,  B23K26/364

CPC classification number: H05K3/0026 ,  B23K26/364 ,  B23K26/38 ,  B23K26/402 ,  B23K2103/172 ,  H05K3/0052 ,  H05K2201/09845 ,  H05K2203/0346 ,  H05K2203/107

Abstract: Systems and techniques are provided for trench cutting with laser machining. A laminate material including a conductive layer and a non-conductive layer may be cut with a first cut using a UV-laser. The cutting of a second cut, using the UV-laser, may be started at a top electrode of the non-conductive layer based on the location of the first cut, wherein the second cut is wider than the first cut. The cutting of the second cut may be stopped partially though the non-conductive layer. The stopping of the cutting of the second cut partially though the non-conductive layer may include stopping the cutting of the second cut before cutting a bottom electrode of the non-conductive layer.

公开(公告)号：US20170231099A1

公开(公告)日：2017-08-10

申请号：US15017165

申请日：2016-02-05

Applicant: Dell Products, LP

Inventor： Kevin W. Mundt ,  Sandor Farkas

IPC: H05K3/40 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K3/4084 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/09845 ,  H05K2203/0207 ,  H05K2203/175

Abstract: An electrical break is created in a via that would ordinarily electrically connect different layers of a printed circuit board. The electrical break severs the via into two or more separate and electrically disconnected vias. The electrical break may be placed at any depth along the via, thus demarking different purposes associated with different layers.