公开(公告)号：US10064287B2

公开(公告)日：2018-08-28

申请号：US14533448

申请日：2014-11-05

Applicant: Infineon Technologies Austria AG

Inventor： Martin Standing ,  Andrew Roberts

IPC: H05K1/00 ,  H05K3/32 ,  H05K1/14 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/32 ,  H05K1/0204 ,  H05K1/0209 ,  H05K1/141 ,  H05K1/144 ,  H05K1/185 ,  H05K2201/041

Abstract: In an embodiment, a method includes arranging a first carrier on a first major surface of a circuit board such that an electronic component arranged on the first carrier is positioned in an aperture in the circuit board and spaced apart from side walls of the aperture, and arranging a second carrier on a second major surface of the circuit board such that the second carrier covers the electronic component and the aperture, the second major surface of the circuit board opposing the first major surface of the circuit board. The electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact pad arranged on a first major surface of the dielectric core layer.

公开(公告)号：US20180217691A1

公开(公告)日：2018-08-02

申请号：US15325291

申请日：2016-12-01

Applicant: Lei Cui

Inventor： Lei Cui

IPC: G06F3/041 ,  H05K1/11 ,  H01L27/12 ,  H05K3/36 ,  H05K1/14

CPC classification number: G06F3/041 ,  G06F2203/04102 ,  G06F2203/04103 ,  H01L27/1218 ,  H01L27/1248 ,  H05K1/118 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/041 ,  H05K2201/10128 ,  H05K2201/10151 ,  H05K2201/10166

Abstract: A flexible touch screen includes a flexible substrate having a main outer lead bonding area and a touch lead bonding area provided with flexible-printed-circuit-board bonding pads; and a touch control panel connected to the flexible substrate via an adhesive layer. The touch control panel has a surface facing the flexible substrate and having a touch-control flexible circuit board mounted thereon. The touch-control flexible circuit board corresponds to the touch lead bonding area in position. In bonding of flexible circuit boards, the touch-control flexible circuit board of the touch control panel is bonded to the flexible-printed-circuit-board bonding pads in the touch lead bonding area; the flexible substrate is bonded to a main flexible circuit board via the flexible-printed-circuit-board bonding pads in the main outer lead bonding area. The FPC bonding process for the flexible touch screen is simplified, and the number of FPC is reduced.

公开(公告)号：US20180168045A1

公开(公告)日：2018-06-14

申请号：US15836860

申请日：2017-12-09

Applicant: CYNTEC CO., LTD.

Inventor： BAU-RU LU ,  CHUN HSIEN LU ,  DA-JUNG CHEN

IPC: H05K1/18 ,  H05K1/14 ,  H05K1/11

CPC classification number: H01F27/022 ,  H01F17/04 ,  H01F27/24 ,  H01F27/28 ,  H01F27/2823 ,  H01F27/32 ,  H01F27/36 ,  H01F41/00 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/041 ,  H05K2201/09063 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10545

Abstract: An electronic module is disclosed, wherein the electronic module comprises: a module board and a connection board, wherein a plurality of first electronic devices are disposed over a top surface of the module board, and a plurality of second electronic devices are disposed on a bottom surface of the module board, wherein a plurality of first contact points are disposed on the bottom surface of the module board and electrically connected to a plurality of second contact points on a top surface of the connection board, wherein a plurality of third contact points are on a bottom surface of the connection board for connecting with an external circuit.

公开(公告)号：US09997491B2

公开(公告)日：2018-06-12

申请号：US14406958

申请日：2014-04-16

Applicant: Sony Corporation

Inventor： Takeshi Ichimura

IPC: H05K3/30 ,  H01L23/00 ,  H05K3/34 ,  H05K3/36 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H05K1/14

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3142 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/0665 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H05K1/144 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1105 ,  H05K2203/1305 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures.

公开(公告)号：US09991621B2

公开(公告)日：2018-06-05

申请号：US14896420

申请日：2014-05-15

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Konrad Wagner ,  Jürgen Holz

IPC: H05K7/00 ,  H01R13/405 ,  H05K1/14 ,  H01R4/24 ,  H01R12/71 ,  H01R24/58 ,  H05K1/03 ,  H05K1/18 ,  H05K7/02 ,  H05K1/05 ,  H05K3/36 ,  H05K3/32

CPC classification number: H01R13/405 ,  H01R4/2404 ,  H01R4/2479 ,  H01R12/718 ,  H01R24/58 ,  H05K1/0366 ,  H05K1/038 ,  H05K1/056 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K3/325 ,  H05K3/368 ,  H05K7/02 ,  H05K2201/012 ,  H05K2201/0129 ,  H05K2201/041 ,  H05K2201/10106 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/10409

Abstract: An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface.

公开(公告)号：US09990061B2

公开(公告)日：2018-06-05

申请号：US15452718

申请日：2017-03-07

Applicant: Synaptics Incorporated

Inventor： Joseph Kurth Reynolds ,  Shawn P. Day

IPC: G06F3/0354 ,  H05K1/18 ,  H05K1/02 ,  H05K1/14 ,  H03K17/96 ,  G06F3/044 ,  G06F3/041

CPC classification number: G06F3/03547 ,  G06F3/0412 ,  G06F3/0414 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04102 ,  G06F2203/04107 ,  H03K17/962 ,  H03K2217/960765 ,  H05K1/0201 ,  H05K1/0218 ,  H05K1/0274 ,  H05K1/144 ,  H05K1/189 ,  H05K2201/041 ,  H05K2201/10128 ,  H05K2201/10151

Abstract: A touch sensor device is provided that uses a flexible circuit substrate to provide an improved input device. Specifically, the present invention uses a touch sensor controller affixed to the flexible circuit substrate, which is coupled to a sensor component to provide a flexible, reliable and cost effective touch sensor suitable for a wide variety of applications. In one embodiment the touch sensor uses a flexible circuit substrate that provides relatively high temperature resistance. This allows the touch sensor controller to be affixed using reliable techniques, such as various types of soldering. The sensor component can comprise a relatively low-temperature-resistant substrate that can provide a cost effective solution. Taken together, this embodiment of the touch sensor provides reliability and flexibility at relatively low cost.

公开(公告)号：US09942986B1

公开(公告)日：2018-04-10

申请号：US15400677

申请日：2017-01-06

Applicant: Apple Inc.

Inventor： Koohee Han ,  Hui Chen ,  Kuo-Hua Sung ,  Cyrus Y. Liu ,  To C. Tan

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/10 ,  H05K3/36 ,  H05K3/38

CPC classification number: H05K1/144 ,  H05K1/028 ,  H05K1/09 ,  H05K1/11 ,  H05K3/10 ,  H05K3/365 ,  H05K3/38 ,  H05K2201/041 ,  H05K2203/10

Abstract: Components may have substrates with metal traces that form mating contacts. The components may be bonded together using anisotropic conductive adhesive bonding techniques. During bonding, conductive particles may be concentrated over the contacts by application of magnetic or electric fields or by using a template transfer process. Gaps between the contacts may be at least partially free of conductive particles to help isolate adjacent contacts. Polymer between the substrates may attach the substrates together. The conductive particles may be embedded in the polymer and crushed or melted to short opposing contacts together.

公开(公告)号：US20180068957A1

公开(公告)日：2018-03-08

申请号：US15796523

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC: H01L23/552 ,  H01L23/367 ,  H05K1/16 ,  H01L25/16 ,  H05K1/14 ,  H05K1/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/64 ,  H01L23/50 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H02J7/0042 ,  H02J7/0052 ,  H02J7/345 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/144 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/0999 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/014 ,  H01L2924/00

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

公开(公告)号：US20180031938A1

公开(公告)日：2018-02-01

申请号：US15661443

申请日：2017-07-27

Applicant: Japan Display Inc.

Inventor： Yoshihiro WATANABE ,  Yoshikatsu IMAZEKI ,  Yoichi KAMIJO ,  Shuichi OSAWA

IPC: G02F1/1362 ,  G02F1/1339 ,  H05K3/36 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  G02F1/1333 ,  H05K1/14

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/133528 ,  G02F1/1339 ,  G02F1/134363 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/42 ,  H05K1/115 ,  H05K1/144 ,  H05K3/002 ,  H05K3/0026 ,  H05K3/366 ,  H05K3/4038 ,  H05K2201/041 ,  H05K2201/09036 ,  H05K2201/09827 ,  H05K2201/10136 ,  H05K2203/107

Abstract: According to one embodiment, an electronic apparatus includes a first substrate, a second substrate, and a connecting material. The second substrate includes a second basement and a second conductive layer. The second basement has a third surface opposed to the first conductive layer and a fourth surface and is spaced apart from the first conductive layer. The second substrate has a first hole penetrating the second basement. The first substrate has a second hole. A third opening of the second hole is smaller than a first opening of the first hole. A connecting material connects the first conductive layer and the second conductive layer via the first hole.

公开(公告)号：US20170354031A1

公开(公告)日：2017-12-07

申请号：US15172102

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Jeffory L. Smalley ,  Jonathan W. Thibado

IPC: H05K1/02 ,  H01L23/00 ,  H01L25/065 ,  H05K1/14 ,  H05K3/36 ,  H05K1/18 ,  H05K3/34 ,  H01L23/498 ,  G06F1/16

CPC classification number: H05K1/0271 ,  G06F1/16 ,  G06F1/206 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15323 ,  H05K1/0212 ,  H05K1/144 ,  H05K1/181 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/10189 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.