公开(公告)号：US11683890B2

公开(公告)日：2023-06-20

申请号：US16227243

申请日：2018-12-20

Applicant: INTEL CORPORATION

Inventor： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh ,  Mohanraj Prabhugoud

IPC: H05K3/34 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  G06F1/16 ,  H01L23/498

CPC classification number: H05K3/3494 ,  G06F1/16 ,  H01L23/49816 ,  H05K1/0201 ,  H05K1/0212 ,  H05K1/112 ,  H05K1/181 ,  H05K3/3421 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.

公开(公告)号：US11658106B2

公开(公告)日：2023-05-23

申请号：US17183405

申请日：2021-02-24

Applicant: FUJITSU LIMITED

Inventor： Kenichi Kawai

IPC: H05K1/18 ,  H01L23/498 ,  G06F30/394 ,  H01L23/64 ,  G06F115/12

CPC classification number: H01L23/49838 ,  G06F30/394 ,  H01L23/642 ,  H05K1/181 ,  G06F2115/12 ,  H01L23/49816 ,  H01L23/49822 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: An electronic device includes: a board that includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads which are provided in the insulating film so as to surround a capacitor region in which a capacitor is provided and to which a plurality of bumps is coupled; and an electronic component that is mounted at the board, and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via. Further, a method for supporting design of the electronic device is provided.

公开(公告)号：US11652062B2

公开(公告)日：2023-05-16

申请号：US16706563

申请日：2019-12-06

Applicant: FARADAY SEMI, INC.

Inventor： Parviz Parto

IPC: H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H01L49/02 ,  H02M3/158 ,  G06F1/3287 ,  H01L21/48 ,  H01L23/498 ,  H02M1/08 ,  H02M1/00

CPC classification number: H01L23/5389 ,  G06F1/3287 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L28/10 ,  H02M3/158 ,  H02M3/1584 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/007 ,  H02M1/08 ,  H05K2201/10378

Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.

公开(公告)号：US20190246488A1

公开(公告)日：2019-08-08

申请号：US16370506

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Evan Piotr Kuklinski ,  Jerrod Peterson ,  Ruander Cardenas ,  Patrick Douglas James

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0203 ,  F28F2013/006 ,  H05K1/181 ,  H05K2201/066 ,  H05K2201/10159 ,  H05K2201/10265 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable an active loading mechanism. The electronic device can include a printed circuit board, a heat source located on the printed circuit board, and an active loading mechanism secured to the printed circuit board. The active loading mechanism is over the heat source and includes shape memory material. When the shape memory material is not activated, the active loading mechanism applies a first load on the heat source and when the shape memory material is activated, the active loading mechanism applies a second load on the heat source.

公开(公告)号：US20190098762A1

公开(公告)日：2019-03-28

申请号：US15713453

申请日：2017-09-22

Applicant: Apple Inc.

Inventor： Lan H. Hoang ,  Takayoshi Katahira

IPC: H05K1/18 ,  H05K1/11 ,  H05K7/14

CPC classification number: H05K1/182 ,  H05K1/112 ,  H05K1/118 ,  H05K1/14 ,  H05K1/144 ,  H05K1/145 ,  H05K1/185 ,  H05K1/189 ,  H05K3/4691 ,  H05K7/1422 ,  H05K2201/042 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2203/1316

Abstract: Connectors that allow system-in-package modules to connect to other circuits in an electronic device in an area-efficient manner.

公开(公告)号：US20180350769A1

公开(公告)日：2018-12-06

申请号：US16055734

申请日：2018-08-06

Applicant: FUJIFILM Corporation

Inventor： Kosuke YAMASHITA

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/83 ,  H01L21/76841 ,  H01L21/76877 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/29313 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29366 ,  H01L2224/2937 ,  H01L2224/29379 ,  H01L2224/29381 ,  H01L2224/29384 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H05K3/323 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/10378 ,  H05K2203/0278 ,  H01L2224/81 ,  H01L2224/83

Abstract: An object of the present invention is to provide an anisotropic conductive bonding member capable of achieving excellent conduction reliability and insulation reliability, a semiconductor device using the same, a semiconductor package, and a semiconductor device production method. An anisotropic conductive bonding member of the present invention includes an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof, and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each of the conductive paths has a protrusion protruding from the surface of the insulating base, the protrusion of each of the conductive paths is buried in the pressure sensitive adhesive layer, and the pressure sensitive adhesive layer contains a polymer material and an antioxidant material.

公开(公告)号：US20180295718A1

公开(公告)日：2018-10-11

申请号：US16007410

申请日：2018-06-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/02 ,  H01L23/498 ,  H01R12/71 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

公开(公告)号：US20180286794A1

公开(公告)日：2018-10-04

申请号：US15997849

申请日：2018-06-05

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Pao-Hung Chou ,  Shih-Ping Hsu

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/111 ,  H05K3/061 ,  H05K3/40 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

公开(公告)号：US20180286593A1

公开(公告)日：2018-10-04

申请号：US16002780

申请日：2018-06-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Heung Kil PARK ,  Young Key KIM

IPC: H01G4/30 ,  H01G4/232 ,  H01G2/06 ,  H05K3/34

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/232 ,  H01G4/2325 ,  H05K3/3442 ,  H05K2201/0133 ,  H05K2201/0281 ,  H05K2201/10378 ,  H05K2201/10636 ,  H05K2201/10962 ,  Y02P70/611 ,  Y02P70/613

Abstract: A capacitor component includes a capacitor body including dielectric layers and first and second internal electrodes alternately stacked; and a connection terminal coupled to the capacitor body and including a buffer member having insulating properties and at least one conductive fiber portion penetrating through the buffer member.

公开(公告)号：US20180277492A1

公开(公告)日：2018-09-27

申请号：US15468067

申请日：2017-03-23

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H05K1/181 ,  H05K3/301 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.