公开(公告)号：US09837390B1

公开(公告)日：2017-12-05

申请号：US15344736

申请日：2016-11-07

Applicant: Corning Incorporated

Inventor： Michael Lesley Sorensen ,  Sean Mathew Garner

IPC: H01L25/075 ,  H05K3/10 ,  H05K3/30 ,  H05K3/28 ,  H05K1/18 ,  H01L33/54 ,  H01L33/62 ,  H05K1/11 ,  H01L33/56

CPC classification number: H01L25/0753 ,  H01L24/98 ,  H01L33/20 ,  H01L33/54 ,  H01L33/56 ,  H01L33/62 ,  H01L2933/005 ,  H01L2933/0066 ,  H05K1/115 ,  H05K1/186 ,  H05K3/10 ,  H05K3/284 ,  H05K3/285 ,  H05K3/30 ,  H05K2201/09072 ,  H05K2201/10106 ,  H05K2201/10128 ,  H05K2201/10674 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: Embodiments are related to fluidic assembly and, more particularly, to systems and methods for forming physical structures on a substrate.

公开(公告)号：US20170338172A1

公开(公告)日：2017-11-23

申请号：US15673451

申请日：2017-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki YOSUI ,  Keisuke IKENO ,  Yuki ITO

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81205 ,  H05K1/02 ,  H05K1/0298 ,  H05K3/32 ,  H05K3/46 ,  H05K3/4635 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/0285

Abstract: A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal surface, and at least one first dummy conductor disposed inside the element assembly and being in a floating state. When the element assembly is viewed from a normal direction that is normal to the principal surface, a distance between an m-th external electrode and a nearest external electrode therefrom among the first to the n-th external electrodes is defined as a distance Dm, an average of distances D1 to Dn is defined as an average Dave, and when the element assembly is viewed from the normal direction, an area within a circle with a center on the m-th external electrode and with a radius of Dm is defined as an area Am. The first dummy conductor is located in at least one area Am with a radius of Dm smaller than the average Dave when viewed from the normal direction.

公开(公告)号：US09807882B1

公开(公告)日：2017-10-31

申请号：US15239751

申请日：2016-08-17

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim

IPC: H01L23/48 ,  H05K1/11 ,  H05K3/40 ,  H05K3/30 ,  H05K1/03 ,  H05K1/18 ,  H01F27/28 ,  H05K3/06 ,  H03H7/01 ,  H03H7/46 ,  H01L49/02 ,  H01L23/66 ,  H01Q1/48 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q1/24

CPC classification number: H05K1/181 ,  H01F27/2804 ,  H01L23/49822 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/06 ,  H01L28/10 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01Q1/241 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q1/48 ,  H03H7/0115 ,  H03H7/0138 ,  H03H7/46 ,  H05K1/0224 ,  H05K1/0271 ,  H05K1/144 ,  H05K3/06 ,  H05K3/303 ,  H05K2201/041 ,  H05K2201/045 ,  H05K2201/0715 ,  H05K2201/09136 ,  H05K2201/1003 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: An integrated circuit (IC) device may include a first substrate having an inductor ground plane in a conductive layer of the first substrate. The integrated circuit may also include a first inductor in a passive device layer of a second substrate that is supported by the first substrate. A shape of the inductor ground plane may substantially correspond to a silhouette of the first inductor.

公开(公告)号：US20170303400A1

公开(公告)日：2017-10-19

申请号：US15489563

申请日：2017-04-17

Applicant: Skyworks Solutions, Inc.

Inventor： Darren Roger Frenette ,  George Khoury ,  Leslie Paul Wallis ,  Lori Ann DeOrio

IPC: H05K1/18 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H04B1/40 ,  H03F3/195 ,  H03F3/213 ,  H01L23/66 ,  H03H7/06

CPC classification number: H05K1/181 ,  H01L23/3107 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L25/18 ,  H01L41/0475 ,  H01L41/113 ,  H01L2223/6644 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48225 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/146 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03B5/32 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451 ,  H03H7/06 ,  H03H9/0547 ,  H03H2001/0021 ,  H04B1/40 ,  H05K2201/1006 ,  H05K2201/10098 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A packaged module for use in a wireless communication device has a substrate supporting an integrated circuit die that includes at least a microprocessor and radio frequency receiver circuitry and a stacked filter assembly configured as a filter circuit that is in communication with the radio frequency receiver circuitry. The stacked filter assembly includes a plurality of passive components, where each passive component is packaged as a surface mount device. At least one passive component is in direct communication with the substrate and at least another passive component is supported above the substrate by the at least one passive component that is in the direct communication with the substrate.

公开(公告)号：US20170271288A1

公开(公告)日：2017-09-21

申请号：US15611812

申请日：2017-06-02

Applicant: GE Embedded Electronics Oy

Inventor： Antti Iihola ,  Risto Tuominen

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H05K1/18 ,  H05K3/30

CPC classification number: H01L24/09 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0969 ,  H05K2201/10674 ,  H01L2924/00

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

公开(公告)号：US20170265312A1

公开(公告)日：2017-09-14

申请号：US15606680

申请日：2017-05-26

Applicant: Dyi-Chung HU

Inventor： Dyi-Chung HU

IPC: H05K3/46 ,  H01L21/683 ,  H01L23/00

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K2201/10674

Abstract: A redistribution film for IC package is disclosed, which comprises a top redistribution layer configured on top of a bottom redistribution layer. The top redistribution layer is fabricated following PCB design rule, and the bottom redistribution layer is fabricated following IC design rule. Further, the interface between the top redistribution layer and the bottom redistribution layer is optionally made roughed to increase bonding forces therebetween.

公开(公告)号：US20170261799A1

公开(公告)日：2017-09-14

申请号：US15604877

申请日：2017-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHONG-GUK LEE ,  JOO-YEON WON ,  SE-HUI JANG ,  SU-Ml MOON ,  DONG-WOOK LEE

IPC: G02F1/1345 ,  H01L23/498 ,  H01L27/12 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

公开(公告)号：US09763319B2

公开(公告)日：2017-09-12

申请号：US14706269

申请日：2015-05-07

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K7/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H01L23/538 ,  H01L25/18 ,  H01L23/498

CPC classification number: H05K1/0243 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/18 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0949 ,  H05K2201/09518 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.

公开(公告)号：US20170256479A1

公开(公告)日：2017-09-07

申请号：US15600793

申请日：2017-05-22

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/495 ,  H01L23/60

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/053 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/60 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.

公开(公告)号：US20170236797A1

公开(公告)日：2017-08-17

申请号：US15584498

申请日：2017-05-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H05K3/34 ,  H05K1/11 ,  H01L23/544 ,  H01L23/13

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16238 ,  H01L2224/1705 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.