公开(公告)号：US20180277471A1

公开(公告)日：2018-09-27

申请号：US15994006

申请日：2018-05-31

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/00 ,  H01L23/48 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

公开(公告)号：US10085341B2

公开(公告)日：2018-09-25

申请号：US15461406

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K7/10 ,  H05K1/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/20 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

公开(公告)号：US20180240723A1

公开(公告)日：2018-08-23

申请号：US15958949

申请日：2018-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang

IPC: H01L23/24 ,  H01L21/56 ,  H01L25/10 ,  H01L21/48 ,  H05K1/18 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/24 ,  H01L21/481 ,  H01L21/4885 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/181 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

公开(公告)号：US20180209046A1

公开(公告)日：2018-07-26

申请号：US15878657

申请日：2018-01-24

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan ,  Poh Cheng Ang

IPC: C23C18/16 ,  H01L23/498 ,  C25D5/02 ,  H05K3/18 ,  H05K1/11 ,  H01L21/48 ,  H05K3/46

CPC classification number: C23C18/1653 ,  C23C18/1605 ,  C23C18/1607 ,  C23C18/1657 ,  C25D5/022 ,  H01L21/486 ,  H01L23/49822 ,  H05K1/115 ,  H05K3/184 ,  H05K3/205 ,  H05K3/244 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2201/10378

Abstract: An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

公开(公告)号：US20180190634A1

公开(公告)日：2018-07-05

申请号：US15396434

申请日：2016-12-31

Applicant: Intel IP Corporation

Inventor： Russell S. Aoki ,  Casey G. Thielen

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/544 ,  H05K1/18 ,  H05K3/34 ,  H01L25/065 ,  H01L25/00 ,  H01L23/32 ,  B23K1/00

CPC classification number: H01L25/18 ,  H01L23/32 ,  H01L23/544 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54426 ,  H05K1/0271 ,  H05K1/181 ,  H05K3/341 ,  H05K3/3494 ,  H05K2201/10378 ,  H05K2201/10522 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/11

Abstract: Configurable semiconductor packages and processes to attain a defined configuration are provided. A configurable semiconductor package includes a base semiconductor package including a semiconductor die mounted on a surface of a package substrate. An expansion package can be mechanically coupled to a mounting member. The expansion package includes a second package substrate and one or more second semiconductor dies that can be surface mounted to the second package substrate. The second package substrate include an array of interconnects that permit coupling (mechanically and/or electrically) the second semiconductor die(s) to the package substrate of the base semiconductor package. The mounting member can mechanically attach to the base semiconductor package, resulting in a package assembly that has the array of interconnects adjacent to another array of interconnects in the package substrate of the base semiconductor package. The expansion package can be coupled to the base semiconductor package via the interconnects, providing expanded functionality relative to the functionality of the base semiconductor package.

公开(公告)号：US20180184514A1

公开(公告)日：2018-06-28

申请号：US15807648

申请日：2017-11-09

Applicant: FUJITSU LIMITED

Inventor： Tetsuro Yamada ,  AKIKO MATSUI ,  Mitsuhiko Sugane ,  Takahide Mukoyama ,  YOSHIYUKI HIROSHIMA ,  Kohei Choraku

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00

CPC classification number: H05K1/0213 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H05K1/0265 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K2201/09463 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.

公开(公告)号：US10008480B2

公开(公告)日：2018-06-26

申请号：US15722758

申请日：2017-10-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H05K1/11 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0271 ,  H05K1/11 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10613 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

公开(公告)号：US20180177049A1

公开(公告)日：2018-06-21

申请号：US15380054

申请日：2016-12-15

Applicant: NXP USA, INC.

Inventor： Michael B. Vincent ,  Zhiwei Gong ,  Scott M. Hayes

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/145 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/1178 ,  H05K2203/1316 ,  H05K2203/1327 ,  Y10T29/49165

Abstract: A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.

公开(公告)号：US09991223B2

公开(公告)日：2018-06-05

申请号：US14975532

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Michael R. Hui ,  Jonathon R. Carstens ,  Michael S. Brazel ,  Daniel P. Carter ,  Thomas A. Boyd ,  Shelby A. Ferguson ,  Rashelle Yee ,  Joseph J. Jasniewski ,  Harvey R. Kofstad ,  Anthony P. Valpiani

IPC: B23K3/08 ,  H04L23/00 ,  H01L23/00 ,  B23K1/00 ,  B23K101/42

CPC classification number: H01L24/75 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/42 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/75703 ,  H01L2224/75754 ,  H01L2224/81139 ,  H01L2224/81234 ,  H01L2924/15311 ,  H05K3/325 ,  H05K3/3436 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/166 ,  H05K2203/167 ,  Y02P70/613

Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.

公开(公告)号：US09978705B2

公开(公告)日：2018-05-22

申请号：US15222873

申请日：2016-07-28

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/48 ,  H01L23/00 ,  H05K3/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/20 ,  H05K3/46

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.