公开(公告)号：US20170273193A1

公开(公告)日：2017-09-21

申请号：US15615306

申请日：2017-06-06

Applicant: Eric Sari ,  Brian Stumm ,  Roger Plough

Inventor： Eric Sari ,  Brian Stumm ,  Roger Plough

IPC: H05K3/28 ,  G05B19/042 ,  B65G43/00 ,  B65G37/00

CPC classification number: G05B19/0421 ,  B65G43/00 ,  H05K3/0091 ,  H05K3/28 ,  H05K3/287 ,  H05K2201/09872 ,  H05K2203/1361 ,  H05K2203/1366

Abstract: A unit can include a power supply interface; a processor board power interface operatively coupled to the power supply interface where the processor board power interface operatively couples to and supplies power to a processor board; a serial interface that operatively couples to the processor board; a microcontroller operatively coupled to the serial interface; memory operatively coupled to the microcontroller; a motor control interface operatively coupled to the microcontroller; an optically isolated digital input interface operatively coupled to the microcontroller; a digital output interface operatively coupled to the microcontroller; and instructions stored in the memory and executable by the microcontroller to instruct the unit to receive digital input via the optically isolated digital input interface from a machine and to output motor control signals via the motor control interface to at least one motor of the machine.

公开(公告)号：US20170253765A1

公开(公告)日：2017-09-07

申请号：US15059665

申请日：2016-03-03

Applicant: Motorola Mobility LLC

Inventor： Richard W. Brotzman ,  Ernest Sirois ,  Deborah Paskiewicz

IPC: C09D183/04 ,  H05K1/18

CPC classification number: C09D183/04 ,  C08G77/24 ,  C08G77/80 ,  C09D183/08 ,  H05K1/18 ,  H05K3/282 ,  H05K3/285 ,  H05K2201/0162 ,  H05K2201/09872 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2203/095

Abstract: A polysiloxane film comprises Si—O bonds and has a thickness of 0.3 to 1.5 microns. Adjacent electrodes coated with the polysiloxane film have a leakage current of at most 0.01 mA at 10 V after contact with water. An electrode coated with the polysiloxane film has a contact resistance of at least 0.01 ohms at 1.0 mm of pogo pin compression under a 1.0 N load. The polysiloxane film provides IPx7 protection from ingress of water.

公开(公告)号：US20170027064A1

公开(公告)日：2017-01-26

申请号：US14807594

申请日：2015-07-23

Applicant: International Business Machines Corporation

Inventor： Sarah K. Czaplewski ,  Joseph Kuczynski ,  Jason T. Wertz ,  Jing Zhang

IPC: H05K3/28 ,  H05K3/00 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/28 ,  C09D163/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/0058 ,  H05K3/0079 ,  H05K3/282 ,  H05K3/284 ,  H05K3/288 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/09872 ,  H05K2203/1322

Abstract: In an example, a process for reversibly bonding a conformal coating to a dry film solder mask (DFSM) material is disclosed. The process includes applying a first conformal coating material to a DFSM material. The first conformal coating material includes a first functional group, and the DFSM material includes a second functional group that is different from the first functional group. The process also includes reversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group.

Abstract translation: 在一个实例中，公开了将保形涂层可逆地结合到干膜焊接掩模（DFSM）材料的方法。 该方法包括将第一保形涂层材料施加到DFSM材料。 第一保形涂层材料包括第一官能团，并且DFSM材料包括不同于第一官能团的第二官能团。 该方法还包括通过第一官能团和第二官能团的化学反应将第一共形涂层材料可逆地结合到DFSM材料。

公开(公告)号：US20160338192A1

公开(公告)日：2016-11-17

申请号：US15222333

申请日：2016-07-28

Applicant: Stephen GONYA ,  James Sean EICHE ,  James PATTERSON ,  Kenneth R. TWIGG

Inventor： Stephen GONYA ,  James Sean EICHE ,  James PATTERSON ,  Kenneth R. TWIGG

IPC: H05K1/02 ,  H05K3/06

CPC classification number: H05K1/0284 ,  H05K3/06 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09872

Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.

Abstract translation: 在非平面表面上制造非平面符合电路的方法包括产生第一组一致的层。 通过向表面施加氧化物电介质层，向氧化物介电层施加导电材料层，向导电材料层施加抗蚀剂层，根据期望的电路布局图案化抗蚀剂层，形成第一组一致性层， 蚀刻表面以除去暴露的导电材料，并剥离抗蚀剂层。 该过程可以重复以形成具有通过盲微孔形成的层之间的电连接的多层符合电路。 所得到的一组适形层可以被密封。

公开(公告)号：US20160105970A1

公开(公告)日：2016-04-14

申请号：US14511549

申请日：2014-10-10

Applicant: Lockheed Martin Corporation

Inventor： Stephen Gonya ,  James Sean Eiche ,  James Patterson ,  Kenneth R. Twigg

IPC: H05K3/02 ,  H05K3/28 ,  H05K1/11 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0284 ,  H05K3/06 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09872

Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.

公开(公告)号：US09282630B2

公开(公告)日：2016-03-08

申请号：US13460400

申请日：2012-04-30

Applicant: Nicholas Merz

Inventor： Nicholas Merz

IPC: H05K7/00 ,  H05K1/02 ,  C23C14/08 ,  C23C14/18 ,  H05K3/28

CPC classification number: H05K1/0216 ,  C23C14/086 ,  C23C14/185 ,  H05K3/284 ,  H05K2201/09872

Abstract: Systems and methods for shielding circuitry from interference with conformal coating are disclosed. Systems having conformal EMI shields according to embodiments are provided by applying insulating and conductive layers to areas of a printed circuit board (PCB). This produces systems that may be thinner and also smaller in surface area, and that may be suitable as part of electronic devices.

Abstract translation: 公开了用于屏蔽电路不受保形涂层干扰的系统和方法。 通过将绝缘和导电层施加到印刷电路板（PCB）的区域来提供具有根据实施例的共形EMI屏蔽的系统。 这产生的系统可以更薄并且表面积也更小，并且可以适合作为电子设备的一部分。

公开(公告)号：US09155188B2

公开(公告)日：2015-10-06

申请号：US13631156

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Nicholas G. Merz ,  Hong Wang ,  Michael M. Nikkhoo ,  Dennis R. Pyper ,  Christopher Matthew Werner

IPC: H05K9/00 ,  H05K1/02 ,  H05K3/28

CPC classification number: H05K1/0218 ,  H05K3/284 ,  H05K2201/0317 ,  H05K2201/09618 ,  H05K2201/09872 ,  H05K2201/09909 ,  H05K2201/10371 ,  H05K2201/2018 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.

Abstract translation: 公开了用于制造具有电磁干扰（EMI）屏蔽的印刷电路板（PCB）的方法和装置，并且与传统的框架 - 屏蔽方法相比也具有减小的体积。 一些实施例包括通过将集成电路安装到PCB来制造PCB，通过多个接地通孔来概括对应于集成电路的区域，在PCB上选择性地施加绝缘层，使得接地通孔中的至少一个暴露， 以及选择性地在所述PCB上施加导电层，使得所述导电层覆盖所述集成电路的至少一部分，并且使得所述导电层耦合到暴露的所述接地通孔中的至少一个。

公开(公告)号：US20150282304A1

公开(公告)日：2015-10-01

申请号：US14226593

申请日：2014-03-26

Applicant: Apple Inc.

Inventor： Colin M. Ely ,  Anna-Katrina Shedletsky ,  Fletcher R. Rothkopf ,  Stephen Brian Lynch

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0281 ,  H05K1/028 ,  H05K1/0284 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/115 ,  H05K3/0061 ,  H05K3/28 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/0305 ,  H05K2201/055 ,  H05K2201/057 ,  H05K2201/09109 ,  H05K2201/09872 ,  H05K2201/0999 ,  H05K2201/10128 ,  H05K2201/10409 ,  H05K2201/2009 ,  H05K2203/0126 ,  H05K2203/013 ,  H05K2203/1194 ,  H05K2203/1327 ,  H05K2203/1366

Abstract: An electronic device may be provided with printed circuits. Electrical components may be interconnected using signal paths formed from metal traces in the printed circuits. The printed circuits may include flexible printed circuits with bent configurations. The flexible printed circuits may be provided with integral bend retention structures. A bend retention structure may be formed from a polymer layer, a solder layer, a stiffener formed from metal or polymer that is attached to flexible printed circuit layers with adhesive, a conformal plastic coating that covers exposed metal traces at a bend, a metal stiffener with screw holes, a shape memory alloy, a portion of a flexible printed circuit dielectric substrate layer with a reduced elongation at yield value, or combinations of these structures. The bend retention structure maintains a bend in a bent flexible printed circuit.

Abstract translation: 电子设备可以设置有印刷电路。 电气部件可以使用由印刷电路中的金属迹线形成的信号路径互连。 印刷电路可以包括具有弯曲构型的柔性印刷电路。 柔性印刷电路可以设置有整体弯曲保持结构。 弯曲保持结构可以由聚合物层，焊料层，由金属或聚合物形成的加强件形成，金属或聚合物通过粘合剂附接到柔性印刷电路层，保形塑料涂层覆盖弯曲处的暴露的金属迹线，金属加强件 具有螺孔，形状记忆合金，柔性印刷电路电介质基底层的一部分，屈服值下降的伸长率或这些结构的组合。 弯曲保持结构在弯曲的柔性印刷电路中保持弯曲。

公开(公告)号：US09099567B2

公开(公告)日：2015-08-04

申请号：US14089744

申请日：2013-11-25

Applicant: Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

Inventor： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/00 ,  H05K1/14 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20140292451A1

公开(公告)日：2014-10-02

申请号：US14355900

申请日：2012-12-21

Applicant: Andrew LLC

Inventor： Martin Zimmerman

IPC: H03H7/00

CPC classification number: H03H7/004 ,  H01L2924/0002 ,  H01P5/028 ,  H01Q1/246 ,  H05K1/0225 ,  H05K1/0239 ,  H05K3/28 ,  H05K3/40 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09618 ,  H05K2201/09872 ,  H01L2924/0001

Abstract: A blind-mate capacitive coupling interconnection between a main module enclosure one or more sub-module enclosures has coupling surfaces each with a ground portion and an aperture, an inner element provided in the aperture, spaced away from the ground portion. The coupling surfaces may be provided, for example, as traces on a printed circuit board. To accommodate a degree of mis-alignment, one of the inner elements may be provided larger than the other. Capacitive coupling between the coupling surfaces occurs when the coupling surfaces are mated together, retained in position, for example, by a mechanical fixture.

Abstract translation: 一个或多个子模块外壳之间的主模块外壳之间的盲配电容耦合互连具有各自具有接地部分和开口的耦合表面，设置在孔中的内部元件与接地部分间隔开。 耦合表面可以例如设置在印刷电路板上的迹线上。 为了适应一定程度的误配对，可以将内部元件中的一个设置得大于另一个。 耦合表面之间的电容耦合发生在耦合表面配合在一起时，例如通过机械夹具保持在适当的位置。