公开(公告)号：US08251745B2

公开(公告)日：2012-08-28

申请号：US12186064

申请日：2008-08-05

Applicant: Douglas M. Johnescu ,  Steven E. Minich ,  Stephen B. Smith

Inventor： Douglas M. Johnescu ,  Steven E. Minich ,  Stephen B. Smith

IPC: H01R13/648

CPC classification number: H01R13/6471 ,  H01R12/51 ,  H01R12/7082 ,  H01R12/71 ,  H01R13/514 ,  H01R13/6477 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/325 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10189 ,  H05K2201/1059 ,  Y10T29/49222

Abstract: Disclosed are electrical connectors and methods of assembling an electrical connector having “standard” (i.e., with electrical contacts having in-line tails), jogged (i.e., with electrical contacts having jogged tails but not connected orthogonally to another connector through a substrate), and/or “orthogonal” (i.e., with electrical contacts having jogged tails that are used in an orthogonal application) leadframe assemblies in the same connector. This provides the flexibility of using some of the available contacts in an orthogonal application and, at the same time, having remaining contacts available for routing on the midplane PCB. Though this could be done using only orthogonal leadframe assemblies, the combination of standard leadframe assemblies with orthogonal leadframe assemblies creates additional spacing between the PCB vias, so that signal traces can be more easily routed on the midplane PCB.

Abstract translation: 公开了电连接器和组装电连接器的方法，即具有“标准”（即，具有线内尾部的电触头）的电连接器，具有点动（即，具有慢跑尾部的电触头但未通过基板与另一连接器正交连接） 和/或“正交”（即，具有在正交应用中使用的具有慢跑尾部的电触头）引线框组件在同一连接器中。 这提供了在正交应用中使用一些可用触点的灵活性，并且同时具有可用于在中板PCB上布线的剩余触点。 尽管这可以仅使用正交引线框架组件完成，标准引线框架组件与正交引线框架组合的组合在PCB通孔之间产生了额外的间隔，从而可以更容易地在中板PCB上布线信号迹线。

公开(公告)号：US08143527B2

公开(公告)日：2012-03-27

申请号：US12575863

申请日：2009-10-08

Applicant: Chin-Wen Lo ,  Hsueh-Chih Wu

Inventor： Chin-Wen Lo ,  Hsueh-Chih Wu

IPC: H05K1/00

CPC classification number: H05K1/118 ,  H05K1/117 ,  H05K3/0058 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/09709 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A golden finger for flexible printed circuitboard, comprises: a frame with a tail, being composed of a stiffening plate, a bottom substrate, a bottom copper layer, a cover layer, and a top copper layer while enabling the bottom copper layer to be formed with at least one first routing and at least one second routing, and enabling the top copper layer to be formed with at least one first pin and at least one second pin; at least one first via hole, each being filled with a conductive material and disposed at a position between its corresponding first pin and first routing for connecting the first pin to the first routing electrically; and at least one second via hole, each filled with a conductive material and being disposed at a position between the its corresponding second pin and second routing for connecting the second pin to the second routing electrically.

Abstract translation: 用于柔性印刷电路板的金手指包括：具有尾部的框架，由加强板，底部基板，底部铜层，覆盖层和顶部铜层组成，同时能够形成底部铜层 具有至少一个第一路由和至少一个第二路由，并且使得顶部铜层能够形成有至少一个第一引脚和至少一个第二引脚; 至少一个第一通孔，每个第一通孔都填充有导电材料并且设置在其相应的第一引脚和第一布线之间的位置，用于将第一引脚电连接到第一布线; 以及至少一个第二通孔，每个第二通孔均填充有导电材料，并且设置在其对应的第二引脚和第二布线之间的位置，用于将第二引脚电连接到第二布线。

公开(公告)号：US08130511B2

公开(公告)日：2012-03-06

申请号：US12227059

申请日：2007-05-14

Applicant: Junya Sato ,  Nobuhiro Mikami ,  Shinji Watanabe ,  Atsumasa Sawada ,  Nozomu Nishimura

Inventor： Junya Sato ,  Nobuhiro Mikami ,  Shinji Watanabe ,  Atsumasa Sawada ,  Nozomu Nishimura

IPC: H05K1/11

CPC classification number: H05K3/368 ,  H01L2224/16225 ,  H01R12/61 ,  H01R12/714 ,  H05K1/144 ,  H05K3/365 ,  H05K2201/0314 ,  H05K2201/042 ,  H05K2201/09409 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2203/167

Abstract: A circuit board device, a wiring board connecting method, and a circuit board module device are provided for controlling a compression ratio of anisotropically conductive members within an optimal range, for restraining variations in the impact resilient force of the anisotropically conductive members even if an increased number of wiring boards are laminated, for restraining deformations of the wiring board and fluctuations in the impact resilient force of the anisotropically conductive members even if a static external force or the like is applied, for suppressing a linear expansion of the anisotropically conductive members, even if the ambient temperature changes, to increase the stability of electric connections, and for reducing the impact resilient force of the anisotropically conductive members to allow for a reduction in thickness. The circuit board device comprises wiring boards 101-104, anisotropically conductive members 105 placed between the individual wiring boards, functional blocks 106 separate from anisotropically conductive members 105 and are placed on the same plane as anisotropically conductive members 105 so as to enclose anisotropically conductive members 105, and a pair of holding blocks 107, 108 placed to sandwich wiring boards 101-104. These wiring boards 101-104 are kept compressed while they are clamped between pair of holding blocks 107, 108, so that they are electrically connected with each other by anisotropically conductive members 105.

Abstract translation: 提供电路板装置，布线板连接方法和电路板模块装置，用于控制各向异性导电构件在最佳范围内的压缩比，以便限制各向异性导电构件的冲击弹力的变化，即使增加 为了抑制布线基板的变形以及各向异性导电部件的冲击弹力的波动，即使施加静电外力等，也能够抑制各向异性导电部件的线膨胀，甚至 如果环境温度变化，则增加电连接的稳定性，并且用于减小各向异性导电构件的冲击弹性力以允许减小厚度。 电路板装置包括配线板101-104，放置在各个布线板之间的各向异性导电构件105，与各向异性导电构件105分离的功能块106，并且与各向异性导电构件105放置在同一平面上，以包围各向异性导电构件 105，以及一对夹持布线板101-104的保持块107,108。 这些布线板101-104被夹持在一对保持块107,108之间时被保持压缩，使得它们通过各向异性导电构件105彼此电连接。

公开(公告)号：US20110265322A1

公开(公告)日：2011-11-03

申请号：US13167074

申请日：2011-06-23

Applicant: Robert J. Greenberg ,  Neil Hamilton Talbot ,  Jordan Matthew Neysmith ,  James Singleton Little ,  Brian V. Mech

Inventor： Robert J. Greenberg ,  Neil Hamilton Talbot ,  Jordan Matthew Neysmith ,  James Singleton Little ,  Brian V. Mech

IPC: H05K3/10

CPC classification number: A61N1/0543 ,  A61N1/36046 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/0014 ,  H05K2201/05 ,  H05K2201/053 ,  H05K2201/09063 ,  H05K2201/09409 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49174 ,  Y10T29/49176

Abstract: The present invention provides a flexible circuit electrode array adapted for neural stimulation, comprising: a polymer base layer; metal traces deposited on the polymer base layer, including electrodes suitable to stimulate neural tissue; a polymer top layer deposited on the polymer base layer and the metal traces at least one tack opening. The present invention provides further a method of making a flexible circuit electrode array comprising depositing a polymer base layer; depositing metal on the polymer base layer; patterning the metal to form metal traces; depositing a polymer top layer on the polymer base layer and the metal traces; and preparing at least one tack opening.

Abstract translation: 本发明提供一种适用于神经刺激的柔性电路电极阵列，包括：聚合物基层; 沉积在聚合物基层上的金属痕迹，包括适于刺激神经组织的电极; 沉积在聚合物基层上的聚合物顶层和金属迹线至少一个粘性开口。 本发明还提供一种制造柔性电路电极阵列的方法，包括沉积聚合物基层; 在聚合物基层上沉积金属; 图案化金属以形成金属痕迹; 在聚合物基层和金属迹线上沉积聚合物顶层; 并准备至少一个钉头。

公开(公告)号：US20110032687A1

公开(公告)日：2011-02-10

申请号：US12821957

申请日：2010-06-23

Applicant: Keun-Young SONG

Inventor： Keun-Young SONG

IPC: H05K1/11

CPC classification number: H05K3/361 ,  H05K3/323 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/0949 ,  H05K2201/09781

Abstract: A plasma display device is disclosed. In one embodiment, the device includes 1) a plasma display panel (PDP) configured to display an image, 2) a chassis base having first and second surfaces opposing each other, wherein the first surface of the chassis base supports the PDP and 3) a printed circuit board assembly (PBA) formed on the second surface of the chassis base. The PBA includes i) a plurality of electrode pads formed on a surface of the PBA and ii) a plurality of dummy pads interposed between and not electrically connected to neighboring electrode pads. The device further includes a flexible printed circuit (FPC) configured to electrically connect the PBA and the PDP, wherein the surface of the PBA faces the FPC, wherein the FPC contacts i) at least one of the dummy pads and ii) the electrode pads, and wherein the least one dummy pad and the electrode pads have substantially the same height defined from the surface of the PBA to the FPC.

Abstract translation: 公开了一种等离子体显示装置。 在一个实施例中，该装置包括1）被配置为显示图像的等离子体显示面板（PDP），2）具有彼此相对的第一和第二表面的底架，其中底架的第一表面支撑PDP，以及3） 形成在底座的第二表面上的印刷电路板组件（PBA）。 PBA包括i）形成在PBA的表面上的多个电极焊盘，以及ii）插入在彼此电极焊盘之间并且未电连接到相邻电极焊盘的多个虚拟焊盘。 该装置还包括被配置为电连接PBA和PDP的柔性印刷电路（FPC），其中PBA的表面面向FPC，其中FPC接触i）至少一个虚拟焊盘，以及ii）电极焊盘 ，并且其中所述至少一个虚拟焊盘和所述电极焊盘具有从所述PBA的表面到所述FPC的基本相同的高度。

公开(公告)号：US07798820B2

公开(公告)日：2010-09-21

申请号：US11696559

申请日：2007-04-04

Applicant: Liu Hong

Inventor： Liu Hong

IPC: H01R12/00

CPC classification number: H01R12/721 ,  H01R13/6471 ,  H05K1/117 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/10121

Abstract: An edge connector design for use with a printed circuit board included in a communications module is disclosed. In one embodiment, the edge connector comprises a planar surface defining a terminal end of the printed circuit board, and a plurality of conductive contact pads arranged on the planar surface. The contact pads include first and second ground contact pads disposed adjacent opposite side portions of the planar surface and first and second power contact pads disposed proximate a central portion of the planar surface. First and second pairs of differential transmit data signal contact pads, as well as first and second pairs of differential receive data signal contact pads are also included, the pairs being disposed between one of the ground contact pads and one of the power contact pads. The edge connector is received by a female connector of a host device to connect the module to the host.

Abstract translation: 公开了一种用于与包括在通信模块中的印刷电路板一起使用的边缘连接器设计。 在一个实施例中，边缘连接器包括限定印刷电路板的终端的平坦表面和布置在平坦表面上的多个导电接触垫。 接触焊盘包括邻近平面表面的相对侧部设置的第一和第二接地焊盘，以及靠近平面的中心部分设置的第一和第二电源接触焊盘。 还包括第一对和第二对差分发射数据信号接触焊盘，以及第一和第二对差分接收数据信号接触焊盘，这些对设置在一个接地焊盘和一个电源接触焊盘之间。 边缘连接器由主机设备的母连接器接收，以将模块连接到主机。

公开(公告)号：US20100123144A1

公开(公告)日：2010-05-20

申请号：US12621529

申请日：2009-11-19

Applicant: Tzu-Hao Chao

Inventor： Tzu-Hao Chao

IPC: H01L33/00 ,  H01L23/52

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit structure of a package carrier including a plurality of chip pads, a first electrode, a second electrode, a third electrode and a fourth electrode is provided. These chip pads are arranged in an M×N array. A first bonding pad, a second bonding pad, a third bonding pad and a fourth bonding pad are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S−1)th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the Sth row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The forth electrode is connected with each forth bonding pad.

Abstract translation: 提供了包括多个芯片焊盘，第一电极，第二电极，第三电极和第四电极的封装载体的电路结构。 这些芯片焊盘以M×N阵列排列。 第一接合焊盘，第二接合焊盘，第三接合焊盘和第四接合焊盘顺序地设置在每个芯片焊盘的外围区域中。 第（S-1）行的第一，第二，第三，第四和第四接合焊盘的旋转90度的取向与Sth的第一，第二，第三和第四接合焊盘的取向相等 行。 第一电极与每个第一接合焊盘连接。 第二电极与每个第二接合焊盘连接。 第三电极与每个第三接合焊盘连接。 第四电极与每个第四接合焊盘连接。

公开(公告)号：US20100026408A1

公开(公告)日：2010-02-04

申请号：US12183062

申请日：2008-07-30

Applicant: Jeng-Jye Shau

Inventor： Jeng-Jye Shau

IPC: H01P5/00

CPC classification number: H05K1/181 ,  H05K1/0295 ,  H05K1/117 ,  H05K1/144 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention provides high performance, low power signal transfer methods for linking large numbers of integrated chips into ultra-high capacity circuits; Example application of the present invention including ultra-high capacity memory systems, and router systems.

Abstract translation: 本发明提供了将大量集成芯片连接成超高容量电路的高性能，低功率信号传输方法; 包括超高容量存储器系统和路由器系统的本发明的示例应用。

公开(公告)号：US07656022B2

公开(公告)日：2010-02-02

申请号：US11488185

申请日：2006-07-18

Applicant: Tomoyuki Kubo

Inventor： Tomoyuki Kubo

IPC: H01L23/053 ,  H01L23/48

CPC classification number: H05K3/3484 ,  B41J2/17526 ,  B41J2/1753 ,  B41J2/17559 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/13012 ,  H01L2224/1403 ,  H01L2224/14051 ,  H05K3/1216 ,  H05K3/363 ,  H05K2201/0394 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2203/043 ,  H05K2203/1476 ,  H01L2924/00014

Abstract: A wiring board is provided, where in the case where the wiring board and a piezoelectric element are connected via solder, the strength of connection in the peripheral region of the wiring board can be increased, and it is difficult for a connection defect to occur in the step of connecting the wiring board to the piezoelectric element. In addition, a manufacturing method for this wiring board is provided. The area of attaching portions 27b provided in the peripheral region of an insulating film 20 is made greater than that of attaching portions 27a provided in the inward region. In addition, the thickness of solder bumps 25b which are formed by providing solder to attaching portions 27b is made substantially the same as the thickness of solder bumps 25a which are formed by providing solder to attaching portions 27a.

Abstract translation: 提供了一种布线板，其中在布线板和压电元件通过焊料连接的情况下，可以增加布线板的周边区域中的连接强度，并且难以发生连接缺陷 将布线板连接到压电元件的步骤。 此外，还提供了一种用于该布线板的制造方法。 设置在绝缘膜20的周边区域中的安装部分27b的面积大于设置在向内区域中的附接部分27a的面积。 此外，通过向附着部分27b提供焊料形成的焊料凸块25b的厚度与通过向附着部分27a提供焊料形成的焊料凸块25a的厚度基本相同。

公开(公告)号：US07646611B2

公开(公告)日：2010-01-12

申请号：US12021419

申请日：2008-01-29

Applicant: Emiko Tani ,  Yasuto Ishimaru ,  Toru Mizutani

Inventor： Emiko Tani ,  Yasuto Ishimaru ,  Toru Mizutani

IPC: H01R9/00

CPC classification number: H01L23/49572 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/118 ,  H05K2201/09409 ,  H05K2201/09727 ,  H05K2201/10681 ,  H05K2203/1545 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A plurality of wiring patterns are formed so as to extend in parallel with each other. A plurality of test terminals are formed in a substantially rectangular shape such that respective widths thereof increase toward respective one sides from respective ends of the plurality of wiring patterns. The plurality of test terminals in each group are arranged so as to be aligned along a length direction of the wiring patterns. The wiring patterns are formed so as to be longer in the order, and the test terminals are further away from a mounting region in the order. An interval (width of a plating resist) between the test terminals in each group and the wiring patterns in the other group adjacent thereto is set to decrease in the order.

Abstract translation: 多个布线图案形成为彼此平行地延伸。 多个测试端子形成为大致矩形形状，使得其各自的宽度从多个布线图案的各个端部朝向相应的一侧增大。 每组中的多个测试端子被布置成沿着布线图案的长度方向排列。 布线图形按照顺序形成为更长，并且测试端子依次进一步远离安装区域。 每组中的测试端子之间的间隔（电镀抗蚀剂的宽度）和与其相邻的另一组中的布线图案按顺序设置为减小。