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    MULTI-LAYERED PRINTED CIRCUIT BOARD HAVING CORE LAYERS INCLUDING INDICIA
    52.
    发明申请
    MULTI-LAYERED PRINTED CIRCUIT BOARD HAVING CORE LAYERS INCLUDING INDICIA 有权
    具有核心层的多层印刷电路板包括印度

    公开(公告)号：US20160037637A1

    公开(公告)日：2016-02-04

    申请号：US14449089

    申请日：2014-07-31

    Applicant: Keysight Technologies, Inc.

    Inventor： Brian Wade Carlson ,  William Hollender ,  Donald Ingram

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H05K1/0269 ,  H05K3/4638 ,  H05K2201/041 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/09936 ,  H05K2203/166

    Abstract: A printed circuit board (PCB) includes a stack of core layers disposed one over another, and electrically conductive interconnects extending vertically in the stack. Each of the core layers includes a substrate having opposite major surfaces, an electrically conductive active trace extending along at least one of the major surfaces, and an indicium. The stack also has an exposed edge where the indicia of the layers are together revealed. The indicia provide identifying and/or fiducial information about the PCB.

    Abstract translation: 印刷电路板（PCB）包括一层叠置的芯层，以及在堆叠中垂直延伸的导电互连。 每个芯层包括具有相反主要表面的基底，沿主要表面中的至少一个延伸的导电活性迹线和标记。 堆叠还具有暴露的边缘，其中层的标记一起显露。 标记提供关于PCB的识别和/或基准信息。

    COMPONENT BUILT-IN MULTILAYER SUBSTRATE FABRICATING METHOD AND COMPONENT BUILT-IN MULTILAYER SUBSTRATE
    53.
    发明申请
    COMPONENT BUILT-IN MULTILAYER SUBSTRATE FABRICATING METHOD AND COMPONENT BUILT-IN MULTILAYER SUBSTRATE 审中-公开
    组件内置多层基板制造方法和组件内置多层基板

    公开(公告)号：US20160007480A1

    公开(公告)日：2016-01-07

    申请号：US14856895

    申请日：2015-09-17

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Kuniaki Yosui

    IPC: H05K3/30 ,  H05K1/02 ,  H01Q1/12 ,  H05K1/18

    CPC classification number: H05K3/30 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01Q1/12 ,  H01Q1/2208 ,  H01Q1/2283 ,  H05K1/165 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/167

    Abstract: A fabricating method according to the present disclosure is a component built-in multilayer substrate fabricating method for incorporating a component (12) in a resin multilayer substrate (11) formed by laminating and pressing thermoplastic resin sheets (111a to 111d) so as to crimp them to each other. With the fabricating method according to the present disclosure, a metal pattern (13) is provided on a component mounting surface of the thermoplastic resin sheet (111a). Further, the component (12) is inserted in the area sandwiched by the metal pattern (13). Out of widths relating to the area sandwiched by the metal pattern (13), the width in the component mounting surface side is assumed to be a width W2, and the width in the component-insertion side is assumed to be a width W3, the width W2 being equal to or larger than a width W1 of the component but less than the width W3.

    Abstract translation: 根据本发明的制造方法是一种组件内置的多层基板的制造方法，用于将部件（12）并入到通过层压和压制热塑性树脂片（111a至111d）而形成的树脂多层基板（11）中以卷曲 他们彼此。 利用根据本公开的制造方法，在热塑性树脂片（111a）的部件安装表面上设置有金属图案（13）。 此外，将组件（12）插入夹在金属图案（13）的区域中。 在与由金属图案（13）夹着的区域相关的宽度之外，元件安装表面侧的宽度被假设为宽度W2，并且元件插入侧的宽度被假设为宽度W3， 宽度W2等于或大于部件的宽度W1但小于宽度W3。

    Reduced EMI with quarter wavelength transmission line stubs
    56.
    发明授权
    Reduced EMI with quarter wavelength transmission line stubs 有权
    使用四分之一波长的传输线存根降低EMI

    公开(公告)号：US09160046B2

    公开(公告)日：2015-10-13

    申请号：US14135131

    申请日：2013-12-19

    Applicant: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.

    Inventor： Eric R. Ao ,  Donald R. Dignam ,  Stephen J. Flint ,  Jian Meng

    IPC: H03H7/01 ,  H01P1/212 ,  H01P3/10

    CPC classification number: H01P1/212 ,  H01P1/2039 ,  H01P3/085 ,  H01P3/10 ,  H05K1/0251 ,  H05K2201/09781

    Abstract: Embodiments of the present invention provide for a transmission circuit that includes a transmission line and a conductive via. The transmission line is electrically coupled to a first conductive via and a second conductive via. The first conductive via includes a first via stub, wherein the transmission line is configured to transmit a signal that is coupled to the first conductive via, and wherein the first via stub extends beyond the transmission line. The second conductive via includes a second via stub, wherein the transmission line is configured to transmit a signal that is coupled to the second conductive via, and wherein the second via stub extends beyond the transmission line. A transmission line stub is electrically coupled to the transmission line or to at least one of the conductive vias, wherein the length of the transmission line stub is configured to suppress a preselected frequency.

    Abstract translation: 本发明的实施例提供一种包括传输线和导电通孔的传输电路。 传输线电耦合到第一导电通孔和第二导电通孔。 第一导电通孔包括第一通孔短路，其中传输线被配置为传输耦合到第一导电通孔的信号，并且其中第一通路短路延伸超过传输线。 第二导电通孔包括第二通路短路，其中传输线被配置为传输耦合到第二导电通孔的信号，并且其中第二通路短线延伸超过传输线。 传输线短截线电耦合到传输线或至少一个导电通孔，其中传输线短截线的长度被配置为抑制预选频率。

    COMPONENT PACKAGE INCLUDING MATCHING CIRCUIT AND MATCHING METHOD THEREOF
    57.
    发明申请
    COMPONENT PACKAGE INCLUDING MATCHING CIRCUIT AND MATCHING METHOD THEREOF 有权
    组件包括匹配电路及其匹配方法

    公开(公告)号：US20150270822A1

    公开(公告)日：2015-09-24

    申请号：US14478295

    申请日：2014-09-05

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Dong Min KANG ,  Seong Il KIM ,  Sang Heung LEE ,  Chull Won JU ,  Ho Kyun AHN ,  Hyung Sup YOON ,  Jong Won LIM

    IPC: H03H7/38

    CPC classification number: H03H7/38 ,  H01L23/642 ,  H01L2224/49175 ,  H01P1/2039 ,  H01P5/12 ,  H05K1/025 ,  H05K2201/09781

    Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.

    Abstract translation: 本文提供了一种包括匹配单元及其匹配方法的组件封装，所述匹配单元包括：衬底; 形成在所述基板上的传输线，所述传输线连接到所述部件封装的端子; 电连接所述传输线和中心部件的接合线; 以及具有通过布线连接与传输线电连接的多个电容器的电容器单元，其中匹配单元的电感通过调整接合线的长度而变化，并且匹配单元的电容可通过增加或减小而变化 通过延长或切断布线连接，在电容器单元内的电容器之间电连接到传输线的电容器的数量。

    DISPLAY DEVICE
    58.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20150228706A1

    公开(公告)日：2015-08-13

    申请号：US14490467

    申请日：2014-09-18

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Hee-Kwon Lee

    IPC: H01L27/32 ,  G02F1/1368 ,  G02F1/1335 ,  H05K1/02 ,  H05K1/11

    CPC classification number: G02F1/1368 ,  G02F1/13452 ,  H01L27/3241 ,  H01L27/3244 ,  H05K1/0245 ,  H05K1/117 ,  H05K1/189 ,  H05K2201/09409 ,  H05K2201/09481 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2201/10128

    Abstract: A display device according to an example embodiment of the present invention includes a display panel configured to display an image, the display panel including a plurality of pixels, a chip on film (COF) coupled to the display panel, the COF comprising a driver, a plurality of COF wires and a plurality of COF pads, and a flexible printed circuit board (FPCB) coupled to the COF, the FPCB including a plurality of FPCB wires and a plurality of FPCB pads, wherein the plurality of COF pads are arranged in two rows, and wherein one or more COF pads of the plurality of COF pads in a first row of the two rows are one or more dummy pads.

    Abstract translation: 根据本发明的示例性实施例的显示装置包括被配置为显示图像的显示面板，包括多个像素的显示面板，耦合到显示面板的薄膜（COF），包括驱动器的COF， 多个COF线和多个COF垫，以及耦合到COF的柔性印刷电路板（FPCB），所述FPCB包括多个FPCB布线和多个FPCB垫，其中所述多个COF垫布置在 两排，并且其中两行中的第一行中的多个COF焊盘中的一个或多个COF焊盘是一个或多个虚拟焊盘。

    Manufacturing method of circuit board
    59.
    发明授权
    Manufacturing method of circuit board 有权
    电路板的制造方法

    公开(公告)号：US09084342B2

    公开(公告)日：2015-07-14

    申请号：US13846871

    申请日：2013-03-18

    Applicant: Unimicron Technology Corp.

    Inventor： Chen-Chuan Chang

    IPC: H05K3/00 ,  H05K3/42 ,  H05K3/10 ,  H05K3/06 ,  H05K3/46 ,  H05K1/18

    CPC classification number: H05K3/007 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/062 ,  H05K3/108 ,  H05K3/428 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/09127 ,  H05K2201/09781 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49156

    Abstract: A manufacturing method of a circuit board is provided. Providing a substrate, where a first laser resistant structure is disposed on a first dielectric layer and at the periphery of a pre-removing area, a second dielectric layer covers the first laser resistant structure, a circuit layer is disposed on the second dielectric layer, a second laser resistant structure is disposed on the second dielectric layer and at the periphery of the pre-removing area, a third dielectric layer covers the circuit layer and the second laser resistant structure. There are gaps between the second laser resistant structure and the circuit layer, and the vertical projection of the gaps on the first dielectric layer overlaps the first laser resistant structure. A laser machining process is performed to etch the third dielectric layer at the periphery of the pre-removing area. The portion of the third dielectric layer within the pre-removing area is removed.

    Abstract translation: 提供电路板的制造方法。 提供一种基板，其中第一耐光结构设置在第一电介质层上并在预除去区域的周围，第二介电层覆盖第一耐光结构，电路层设置在第二介电层上， 第二激光结构被设置在第二介质层上，并且在预除去区域的周围，第三介电层覆盖电路层和第二激光结构。 第二激光电阻结构和电路层之间存在间隙，并且第一电介质层上的间隙的垂直投影与第一耐磨结构重叠。 执行激光加工处理以在预除去区域的周边蚀刻第三介电层。 除去去除区域内的第三电介质层的部分。

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