公开(公告)号：US07705420B2

公开(公告)日：2010-04-27

申请号：US11122038

申请日：2005-05-05

Applicant: Mojtaba Joodaki

Inventor： Mojtaba Joodaki

IPC: H01L29/86

CPC classification number: H01L21/76838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01P11/003 ,  H05K1/024 ,  H05K3/0017 ,  H05K3/28 ,  H05K2201/0394 ,  H01L2924/00

Abstract: A component having at least one conductor path on a substrate, and a production method for fabricating such a component is provided. The component is made by providing at least one conductor path on a predefined area of the substrate. Then a dielectric insulating layer is formed over the at least one conductor path, and a an area of the substrate is completely back etched below the at least one conductor path beginning on the bottom side of the substrate in such a way that the at least one conductor path is supported across the completely back-etched area of the substrate by adhesion to the second insulating layer.

Abstract translation: 提供了在基板上具有至少一个导体路径的部件和用于制造这种部件的制造方法。 该部件通过在基板的预定区域上提供至少一个导体路径而制成。 然后在所述至少一个导体路径上形成介电绝缘层，并且所述基板的一个区域被完全地背面蚀刻在所述至少一个导体路径的下面，从所述基板的底侧开始，使得所述至少一个 通过粘附到第二绝缘层，导体路径被支撑在衬底的完全背面蚀刻的区域上。

公开(公告)号：US07699438B2

公开(公告)日：2010-04-20

申请号：US11426424

申请日：2006-06-26

Applicant: Tomoyuki Kubo

Inventor： Tomoyuki Kubo

IPC: B41J2/14

CPC classification number: B41J2/14201 ,  B41J2002/14491 ,  H05K3/281 ,  H05K3/363 ,  H05K2201/0394 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10477

Abstract: A plurality of land sections, each enclosed by two slits, are formed in a ground wire provided on a side of a flexible wiring board to which a piezoelectric element is connected. Since the ground wire and the land sections are connected by only a thin connection section, the solder deposited on the land sections does not flow to the ground wire.

Abstract translation: 在设置在连接有压电元件的柔性布线基板的一侧的接地线中形成有由两个狭缝围成的多个陆部。 由于接地线和接地部分仅通过薄的连接部分连接，所以沉积在接地部分上的焊料不会流到接地线。

公开(公告)号：US20100044237A1

公开(公告)日：2010-02-25

申请号：US12426276

申请日：2009-04-19

Applicant: CHUNG-JEN TSAI ,  YU-CHENG HUANG ,  HUNG-YI CHANG ,  CHENG-HSIEN LIN

Inventor： CHUNG-JEN TSAI ,  YU-CHENG HUANG ,  HUNG-YI CHANG ,  CHENG-HSIEN LIN

IPC: C25D5/02 ,  C25D7/00

CPC classification number: H05K3/427 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/025 ,  H05K2203/0346

Abstract: A method for manufacturing a PCB is related. The method includes providing a substrate with two opposite conductive layers and defining a through hole passing through the two conductive layers; forming a first electrically conductive metal layer on an inner surface of the substrate in the through hole using an electro-less plating process; forming a second electrically conductive metal layer on the first electrically conductive metal layer using an electro-plating process till the through hole being filled.

Abstract translation: 涉及PCB的制造方法。 该方法包括向基板提供两个相对的导电层并限定穿过两个导电层的通孔; 使用无电镀工艺在所述通孔中的所述基板的内表面上形成第一导电金属层; 在所述第一导电金属层上使用电镀工艺形成第二导电金属层，直到所述通孔被填充。

公开(公告)号：US07667480B2

公开(公告)日：2010-02-23

申请号：US12093232

申请日：2006-11-08

Applicant: Yasuhiro Okuda ,  Akihisa Hosoe ,  Taro Fujita

Inventor： Yasuhiro Okuda ,  Akihisa Hosoe ,  Taro Fujita

IPC: G01R31/02

CPC classification number: H01R13/03 ,  H01R4/04 ,  H01R11/01 ,  H01R43/0235 ,  H01R43/0249 ,  H01R43/0256 ,  H05K3/0035 ,  H05K3/326 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0156 ,  Y10T29/49204

Abstract: Provided is an anisotropic conductive sheet (8) having heat resistance and cold resistance and suitable for connection of electrodes. The anisotropic conductive sheet of the present invention has conductivity in the thickness direction, wherein the base film (1), which is a film made of synthetic resin having an electrical insulation property, has a plurality of holes (3) formed in the thickness direction, and the holes (3) are open to one main surface of the base film and closed to the other main surface, wherein a metal is adhered to the closed parts (2a) and the inner walls (2b) of the holes (3) so that by contacting electrodes (7) with the closed parts (2a) respectively from the outside, the electrodes (7) can electrically be connected through the adhered metal to the main surface where the holes (3) are open.

Abstract translation: 提供具有耐热性和耐寒性并适合于连接电极的各向异性导电片（8）。 本发明的各向异性导电片在厚度方向上具有导电性，其中，作为由具有电绝缘性的合成树脂制成的膜的基膜（1）具有沿厚度方向形成的多个孔（3） 并且孔（3）对基膜的一个主表面开放并且与另一个主表面闭合，其中金属粘附到孔（3）的封闭部分（2a）和内壁（2b） 使得通过从外部分别将电极（7）与闭合部分（2a）接触，电极（7）可以通过粘附的金属电连接到孔（3）打开的主表面。

公开(公告)号：US20090315855A1

公开(公告)日：2009-12-24

申请号：US12485615

申请日：2009-06-16

Applicant: Harutoshi OIKAWA ,  Kiyohiro KIMURA

Inventor： Harutoshi OIKAWA ,  Kiyohiro KIMURA

IPC: G06F3/045 ,  H05K1/02

CPC classification number: H05K3/361 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: A flexible printed circuit includes: a flexible substrate extending from a first end section to a second end section, and having an opening or a notch in proximity to the first end section; a first wiring layer extending from the first end section to the second end section so as to avoid the opening or the notch; a second wiring layer extending from the first end section to the second end section so as to block the opening or the notch; a first conductive member being formed opposed to the flexible substrate in relation to the first wiring layer and at least in proximity to the first end section in a region opposed to the first wiring layer, and being electrically connected to the first wiring layer; and a second conductive member electrically connected to the second wiring layer via the opening or the notch.

Abstract translation: 柔性印刷电路包括：柔性基板，其从第一端部延伸到第二端部，并且具有靠近第一端部的开口或凹口; 第一布线层，从第一端部延伸到第二端部，以避免开口或凹口; 第二布线层，其从所述第一端部延伸到所述第二端部，以阻挡所述开口或所述凹口; 第一导电构件，其与所述柔性基板相对于所述第一布线层形成，并且在与所述第一布线层相对的区域中至少靠近所述第一端部，并且电连接到所述第一布线层; 以及通过所述开口或所述凹口与所述第二布线层电连接的第二导电构件。

公开(公告)号：US20090302463A1

公开(公告)日：2009-12-10

申请号：US12136231

申请日：2008-06-10

Applicant: BERNARDO GALLEGOS ,  DONALD C. ABBOTT

Inventor： BERNARDO GALLEGOS ,  DONALD C. ABBOTT

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/108 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/386 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 110, have solder on the top surface, but not on the sidewalls. The sidewalls of the traces are at right angles to the trace top, giving the trace a rectangular cross section. Consequently, the area for attaching stud 223 is maximized. At the same time, the differential plating method of trace metal 203 and through-hole metal 206 allows different metal thicknesses and provides independent control of the trace aspect ratio for low electrical resistance and trace fatigue.

Abstract translation: 具有绝缘基板的半导体器件，具有差分镀金属和选择性焊料。 具有接触柱223的芯片221附着在磁带101上的迹线203上。未被焊接掩模110保护的迹线在顶表面上具有焊料，但不在侧壁上。 迹线的侧壁与轨迹顶部成直角，给出轨迹为矩形截面。 因此，用于安装螺柱223的区域最大化。 同时，痕量金属203和通孔金属206的差分电镀方法允许不同的金属厚度，并且对于低电阻和痕量疲劳提供独立的痕量纵横比的控制。

公开(公告)号：US07617598B2

公开(公告)日：2009-11-17

申请号：US11681964

申请日：2007-03-05

Applicant: Anthony Primavera ,  Steven P. Findell

Inventor： Anthony Primavera ,  Steven P. Findell

IPC: H01K3/10

CPC classification number: H05K1/0271 ,  H05K1/0201 ,  H05K1/0269 ,  H05K1/0272 ,  H05K1/115 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09509 ,  H05K2203/161 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: This document discusses, among other things, a method including providing a laminate having a first conductive layer, a second conductive layer and an insulator between the first and second conductive layers. A hollow conductive via is formed through the insulator, the conductive via electrically connects the first and second conductive layers. At least one conductive trace electrically connects the hollow conductive via to at least one of the first and second conductive layers. The method further includes forming a channel in the insulator adjacent to the hollow conductive via and the channel surrounds the via. Wherein the channel extends at least part way between the first and second conductive layers, the at least one conductive trace bridges the channel, and the via is isolated from the insulator by the surrounding channel formed adjacent to the hollow conductive via. The via is isolated to prevent separation between the hollow conductive via and at least one of the first and second conductive layers, where the insulator is in a swollen condition.

Abstract translation: 本文件尤其涉及一种包括提供在第一和第二导电层之间具有第一导电层，第二导电层和绝缘体的层压体的方法。 通过绝缘体形成中空导电通孔，导电通孔电连接第一和第二导电层。 至少一个导电迹线将中空导电通孔电连接到第一和第二导电层中的至少一个。 该方法还包括在绝缘体中邻近中空导电通孔形成通道，并且通道围绕通孔。 其中通道至少部分地在第一和第二导电层之间延伸，至少一个导电迹线桥接通道，并且通过与中空导电通孔相邻形成的周围通道将通孔与绝缘体隔离。 通孔被隔离以防止中空导电通孔与绝缘体处于膨胀状态的第一和第二导电层中的至少一个之间的分离。

公开(公告)号：US07607222B2

公开(公告)日：2009-10-27

申请号：US11708567

申请日：2007-02-21

Applicant: Myung-Sam Kang

Inventor： Myung-Sam Kang

IPC: H05K3/34 ,  H01L21/00

CPC classification number: H01L23/3114 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/007 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4007 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2203/0361 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic component package and a manufacturing method thereof are disclosed. A method of manufacturing an electronic component package, which includes: forming a protrusion part on a first carrier board; stacking an insulation layer on the first carrier board and forming a circuit pattern, which includes a bonding pad and a solder ball pad, on the surface of the insulation layer; mounting an electronic component on the surface of the insulation layer and electrically connecting the electronic component and the bonding pad; and removing the first carrier board and the protrusion part, allows the mounting of the electronic component with just a single circuit pattern layer.

Abstract translation: 公开了一种电子部件封装及其制造方法。 一种制造电子部件封装的方法，包括：在第一载体板上形成突出部; 在第一载体板上堆叠绝缘层，并在绝缘层的表面上形成包括焊盘和焊球垫的电路图案; 将电子部件安装在所述绝缘层的表面上并电连接所述电子部件和所述焊盘; 并且移除第一载体板和突起部分允许仅使用单个电路图案层来安装电子部件。

公开(公告)号：US07589416B2

公开(公告)日：2009-09-15

申请号：US11420219

申请日：2006-05-24

Applicant: Hajime Kuwajima ,  Masashi Gotoh

Inventor： Hajime Kuwajima ,  Masashi Gotoh

IPC: H01L23/12 ,  H01L23/053

CPC classification number: H05K1/116 ,  H05K1/0293 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09809 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K2203/173

Abstract: To fill a conductive material in an opening portion formed in a base of an electronic component, a groove is formed to surround an opening in an upper conductor, and the upper conductor is divided into a first conductive portion and a second conductive portion surrounding the first conductive portion. A mask is formed such that a conductor to be filled in the opening portion may not contact the second conductive portion. Metal plate is grown from the side of a lower conductor in the opening portion by using the lower conductor as electrode to fill the opening portion with metal plate. The metal plate filled in the opening portion and the upper conductor are joined by plating by using the upper conductor or the lower conductor as electrode.

Abstract translation: 为了填充形成在电子部件的基部中的开口部分中的导电材料，形成沟槽以包围上导体中的开口，并且上导体被分成第一导电部分和围绕第一导体部分的第二导电部分 导电部分。 形成掩模，使得填充在开口部分中的导体可以不接触第二导电部分。 金属板通过使用下导体作为电极从开口部分中的下导体的侧面生长，以用金属板填充开口部分。 填充在开口部分的金属板和上导体通过使用上导体或下导体作为电极通过电镀而接合。

公开(公告)号：US20090223700A1

公开(公告)日：2009-09-10

申请号：US12042897

申请日：2008-03-05

Applicant: Daniel Youngner ,  Son Thai Lu ,  Helen Chanhvongsak ,  Lisa Lust ,  Doug Carlson

Inventor： Daniel Youngner ,  Son Thai Lu ,  Helen Chanhvongsak ,  Lisa Lust ,  Doug Carlson

IPC: H05K1/02 ,  H01B13/00

CPC classification number: H05K3/4644 ,  H05K1/028 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/115 ,  H05K1/167 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/061 ,  H05K3/24 ,  H05K3/30 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4682 ,  H05K2201/0104 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2201/0394 ,  H05K2203/016 ,  H05K2203/0165 ,  H05K2203/0271

Abstract: An approach for making thin flexible circuits. A layer of dielectric may have one or two surfaces coated with metal. The dielectric and the metal may each have a sub-mil thickness. The dielectric may be held in a fixture for fabrication like that of integrated circuits. The metal may be patterned and have components attached. More layers of dielectric and patterned metal may be added to the flexible circuit. Also bond pads and connecting vias may be fabricated in the flexible circuit. The flexible circuit may be cut into a plurality of smaller flexible circuits.

Abstract translation: 制造薄柔性电路的方法。 电介质层可以具有涂覆有金属的一个或两个表面。 电介质和金属可以各自具有亚密尔厚度。 电介质可以保持在类似于集成电路的固定装置中。 金属可以被图案化并且具有附接的部件。 电介质和图案化的金属层可以添加到柔性电路中。 还可以在柔性电路中制造接合焊盘和连接通孔。 柔性电路可以被切割成多个较小的柔性电路。