公开(公告)号：US07750248B2

公开(公告)日：2010-07-06

申请号：US11634170

申请日：2006-12-06

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 包括依次设置的金属箔，电介质层和导体层的电介质结构体，其中金属箔的厚度为10〜40μm，电介质层的厚度为0.3〜5μm，导体 层的厚度为0.3〜10μm。 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔。 电介质层的通孔具有不同的直径，范围为100〜300μm，导体层的通孔的直径大于电介质层的通孔的直径为5〜50μm ，最小通孔间距为100〜350μm。

公开(公告)号：US20100132984A1

公开(公告)日：2010-06-03

申请号：US12629162

申请日：2009-12-02

Applicant: Yuya Narazako ,  Kazunari Sakaki

Inventor： Yuya Narazako ,  Kazunari Sakaki

IPC: H05K1/03 ,  H05K1/16

CPC classification number: H05K1/0216 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09972

Abstract: In order to reduce noise propagating from a digital signal circuit to an analog signal circuit, a multilayer printed circuit board includes a first digital signal circuit formed in a first region of a front surface, a first analog signal circuit formed in a second region of the front surface, a second digital signal circuit formed at a back surface corresponding to the first region, a second analog signal circuit formed at the back surface corresponding to the second region; an analog ground circuit formed between the front surface and the back surface to ground the first analog signal circuit and the second analog signal circuit, and a first digital ground circuit arranged between the first digital signal circuit and the analog ground circuit and a second digital ground circuit arranged between the second digital signal circuit and the analog ground circuit to ground the first digital signal circuit and the second digital signal circuit.

Abstract translation: 为了减少从数字信号电路传播到模拟信号电路的噪声，多层印刷电路板包括形成在前表面的第一区域中的第一数字信号电路，形成在第一区域的第一模拟信号电路 形成在与第一区域对应的背面的第二数字信号电路，形成在与第二区域对应的背面的第二模拟信号电路; 形成在所述前表面和所述后表面之间以将所述第一模拟信号电路和所述第二模拟信号电路接地的模拟接地电路，以及布置在所述第一数字信号电路和所述模拟地电路之间的第一数字接地电路和第二数字接地 布置在第二数字信号电路和模拟地电路之间以将第一数字信号电路和第二数字信号电路接地的电路。

公开(公告)号：US20100126764A1

公开(公告)日：2010-05-27

申请号：US12277165

申请日：2008-11-24

Applicant: William Leon Rugg

Inventor： William Leon Rugg

IPC: H01R12/02 ,  H05K3/32

CPC classification number: H05K1/0215 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H05K2201/09309 ,  H05K2201/10409 ,  H05K2201/10492 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y10T29/49147 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In order to improve signal to noise ratio and reduce electromagnetic interference, it is presently contemplated to connect ground potential on an electronic package mounted to a printed circuit board directly to a commonly grounded surface of a device via an improved die ground lead with a first end connected to an electrical circuit within the electronic package, and a second end extending away from the electronic package and compressively contacting, rather than forming a bonded or soldered connection to, the commonly grounded surface. By way of example and not limitation, the improved die ground lead may be any one of a tie bar, a metal lead, a pogo pin, and a spring. The use of this configuration for the ground connection between the electrical circuit and the commonly grounded surface results in significantly less physical distance than conventional ground paths for electrical circuits within electronic packages.

Abstract translation: 为了提高信噪比并降低电磁干扰，目前预期将安装到印刷电路板的电子封装上的接地电位通过改进的裸片接地引线直接连接到器件的共同接地表面，第一端 连接到电子封装内的电路，以及远离电子封装延伸的第二端，并且压缩地接触而不是形成与通常接地的表面的接合或焊接的连接。 作为示例而非限制，改进的裸片接地引线可以是连接杆，金属引线，弹簧销和弹簧中的任何一个。 使用这种配置用于电路和公共接地表面之间的接地连接导致比电子封装内的电路的传统接地路径显着更少的物理距离。

公开(公告)号：US20100126759A1

公开(公告)日：2010-05-27

申请号：US12409519

申请日：2009-03-24

Applicant: Shih-Chieh Chao ,  Chih-Wen Huang ,  Chun-Lin Liao

Inventor： Shih-Chieh Chao ,  Chih-Wen Huang ,  Chun-Lin Liao

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0373 ,  H05K2201/086 ,  H05K2201/09309

Abstract: A structure of a multi-layer printed circuit board includes a power layer, a ground layer, and a dielectric layer. The dielectric layer is located between the power layer and the ground layer. The dielectric layer has a relative permittivity and a relative permeability, wherein the product of the relative permittivity and the relative permeability substantially decreases along with an increase in frequency within a frequency range.

Abstract translation: 多层印刷电路板的结构包括功率层，接地层和电介质层。 电介质层位于功率层和接地层之间。 电介质层具有相对介电常数和相对磁导率，其中相对介电常数和相对磁导率的乘积随频率范围内频率的增加而显着降低。

公开(公告)号：US07721238B2

公开(公告)日：2010-05-18

申请号：US11231642

申请日：2005-09-21

Applicant: Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

Inventor： Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

Abstract translation: 一种用于输入设计有印刷电路板（PCB）可安装部件的多个不同电路原理图的方法和装置; 提取用于所述多个不同电路原理图的电路拓扑; 将所述提取的电路拓扑转换为固定数量的连接点; 以及生成具有所述固定数量的连接点的可配置电路PCB物理布局图案，使得当位于所述固定数量的连接点中的一个或多个连接点上时所述PCB可安装部件可以实现由所述多个不同电路原理图表示的任何电路。

公开(公告)号：US20100101850A1

公开(公告)日：2010-04-29

申请号：US12277250

申请日：2008-11-24

Applicant: HOU-YUAN CHOU

Inventor： HOU-YUAN CHOU

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0237 ,  H05K1/11 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/49124 ,  Y10T29/49147

Abstract: A printed circuit board includes a signal layer, an insulation layer, and a reference layer. A transmission line is located on the signal layer. A probing pad is located on the transmission line. Two aligned slots defined in opposite sides of the reference layer leaving a connecting portion. The slots and the connecting portion are in vertical alignment with the probing pad. The signal layer, the insulation layer, and the reference layer are configured in a cascading order. An arrangement of the signal layer in relation to the reference layer including the slots and the connecting portion reduces a capacitance effect caused by the probing pad.

Abstract translation: 印刷电路板包括信号层，绝缘层和参考层。 传输线位于信号层上。 探测板位于传输线上。 限定在参考层的相对侧中的两个对准的槽留下连接部分。 槽和连接部分与探测板垂直对准。 信号层，绝缘层和参考层以级联顺序配置。 信号层相对于包括狭缝和连接部分的参考层的布置减小了由探测垫引起的电容效应。

公开(公告)号：US20100101838A1

公开(公告)日：2010-04-29

申请号：US12649038

申请日：2009-12-29

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/02

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为具有15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US20100053013A1

公开(公告)日：2010-03-04

申请号：US12516130

申请日：2007-11-22

Applicant: Takayoshi Konishi ,  Koichi Kondo ,  Satoshi Arai ,  Shigeyoshi Yoshida

Inventor： Takayoshi Konishi ,  Koichi Kondo ,  Satoshi Arai ,  Shigeyoshi Yoshida

IPC: H01Q13/00 ,  G06K19/06 ,  H03H7/01

CPC classification number: H01P1/2005 ,  H01F1/37 ,  H01F10/20 ,  H01P1/203 ,  H01Q15/008 ,  H05K1/0224 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0373 ,  H05K2201/0323 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09781

Abstract: An EBG (Electromagnetic Bandgap) structure includes a magnetic material portion at least in part. It is preferable to arrange the magnetic material portion close to or, if possible, in contact with a conductor forming the EBG structure, for example, at least a portion of a ground conductor, a conductor producing a capacitance, and/or a conductor producing an inductance, such as a via. Examples of the magnetic material portion include a ferrite plating film, a composite magnetic material layer including magnetic powder and resin binder, and the like.

Abstract translation: EBG（电磁带隙）结构至少部分包括磁性材料部分。 优选的是，将磁性材料部分靠近或者如果可能地与形成EBG结构的导体接触，例如，接地导体的至少一部分，产生电容的导体和/或产生导体的导体 电感，如通孔。 磁性材料部分的实例包括铁素体电镀膜，包括磁性粉末和树脂粘合剂的复合磁性材料层等。

公开(公告)号：US07667378B2

公开(公告)日：2010-02-23

申请号：US11856101

申请日：2007-09-17

Applicant: Toyohiro Sakai

Inventor： Toyohiro Sakai

IPC: H01K1/58 ,  H01J1/62

CPC classification number: G02B6/0085 ,  G02B6/005 ,  G02B6/0083 ,  G02F2001/133628 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/09309 ,  H05K2201/10106

Abstract: An illuminating device includes a light source including a light-emitting element, an electrode electrically connected to the light-emitting element, and a heat radiation terminal electrically isolated from the light-emitting element; and a multilayer substrate including a plurality of insulating layers, a plurality of metal layers, an electrically conducting interlayer contact portion, and a heat-conducting interlayer contact portion. The insulating layers include all insulating layer having a mount surface on which the light source is mounted with the electrode and the heat radiation terminal therebetween. The metal layers include an electrically conducting metal layer electrically connected to the electrode and disposed so as to be separated from the light source by the insulating layer having the mount surface and an electrically isolated metal layer electrically isolated from the other metal layers and disposed most distant from the mount surface of all the metal layers. The electrically conducting interlayer contact portion electrically connects the electrode to the electrically conducting metal layer. The heat-conducting interlayer contact portion connects the heat radiation terminal to the electrically isolated metal layer.

Abstract translation: 照明装置包括：光源，包括发光元件，与发光元件电连接的电极;以及与发光元件电隔离的散热端子。 以及包括多个绝缘层，多个金属层，导电性层间接触部和导热性层间接触部的多层基板。 绝缘层包括具有其上安装有光源的安装表面的所有绝缘层，并且其间具有散热端子。 金属层包括电连接到电极的导电金属层，并且被布置成通过具有安装表面的绝缘层和与其它金属层电隔离并且设置得最远的电隔离金属层与光源分离 从所有金属层的安装表面。 导电层间接触部分将电极电连接到导电金属层。 导热层间接触部分将热辐射端子连接到电隔离的金属层。

公开(公告)号：US20100039784A1

公开(公告)日：2010-02-18

申请号：US12522100

申请日：2008-06-04

Applicant: Seiji Hayashi

Inventor： Seiji Hayashi

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/0231 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/0298 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09781 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Abstract translation: 电源端子和半导体集成电路的接地端子通过电容器连接到导体图案。 导体图案通过滤波器连接到不与接地平面和电源平面连接的平面导体。 因此，引起从电源和地之间产生的共模噪声流入平面导体。 这降低了相对地充当天线的在地面和印刷电路板的电源中流动的共模噪声。