公开(公告)号：US08288682B2

公开(公告)日：2012-10-16

申请号：US11863895

申请日：2007-09-28

Applicant: Islam Salama ,  Yonggang Li

Inventor： Islam Salama ,  Yonggang Li

IPC: B23K26/38

CPC classification number: H05K3/0035 ,  H05K1/116 ,  H05K3/107 ,  H05K2201/09845 ,  H05K2203/108

Abstract: A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via.

Abstract translation: 公开了一种在衬底上形成至少一个微通孔的方法。 该方法包括通过使用第一激光束在衬底中钻取至少一个孔。 第一激光束具有在第一激光束的边缘处比在第一激光束的中心更多的能量分布。 该方法还包括通过使用第二激光束去除衬底的至少一部分，在衬底的顶表面上并围绕至少一个孔的外周形成至少一个坯料图案。 多个空白图案中的至少一个空白图案对应于至少一个微孔的垫。 此后，该方法包括用导电材料填充多个坯料图案和至少一个微通孔，以形成至少微通孔。

公开(公告)号：US08268717B2

公开(公告)日：2012-09-18

申请号：US13209456

申请日：2011-08-15

Applicant: Jing-Hong Yang

Inventor： Jing-Hong Yang

IPC: H01L21/44

CPC classification number: H05K3/4007 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/054 ,  H05K2203/0597

Abstract: A manufacturing method of a bump structure with an annular support includes the following steps. A substrate including pads and a passivation layer is provided. The passivation has first openings exposing a portion of the pads. An UBM material layer is formed to cover the passivation layer and the pads. A patterned photoresist layer, having second openings respectively exposing the UBM material layer over the pads, is formed on the UBM material layer. A diameter of each second opening located on a lower surface of the patterned photoresist layer is less than that located on an upper surface of the patterned photoresist layer. Bumps are formed in the second openings. A portion of the patterned photoresist layer is removed to form an annular support at a periphery of each bump. The UBM material layer is patterned using the annular supports and the bumps as masks to form UBM layers.

Abstract translation: 具有环形支撑件的凸块结构的制造方法包括以下步骤。 提供了包括焊盘和钝化层的衬底。 钝化具有暴露一部分焊盘的第一开口。 形成UBM材料层以覆盖钝化层和焊盘。 在UBM材料层上形成具有分别将UBM材料层暴露在焊盘上的第二开口的图案化光致抗蚀剂层。 位于图案化光致抗蚀剂层的下表面上的每个第二开口的直径小于位于图案化光致抗蚀剂层的上表面上的每个第二开口的直径。 在第二开口中形成凸起。 去除图案化光致抗蚀剂层的一部分以在每个凸起的周边形成环形支撑。 UBM材料层使用环形支撑件和凸块作为掩模来图案化以形成UBM层。

公开(公告)号：US08263871B2

公开(公告)日：2012-09-11

申请号：US12620216

申请日：2009-11-17

Applicant: Hiroshi Asami ,  Osamu Yamagata

Inventor： Hiroshi Asami ,  Osamu Yamagata

IPC: H05K1/00 ,  H01L23/34

CPC classification number: H05K1/0203 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/16195 ,  H01L2924/19105 ,  H05K1/117 ,  H05K2201/066 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10371 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A mount board includes a laminated wiring section including a plurality of wiring layers formed on a surface of a substrate in a laminated manner, wherein a portion of an inner wiring layer is exposed to the outside, the inner wiring layer being any of the plurality of wiring layers excluding an uppermost wiring layer.

Abstract translation: 一种安装板包括层叠布线部分，其包括以层叠的方式形成在基板的表面上的多个布线层，其中内部布线层的一部分暴露于外部，内部布线层是多个 不包括最上面布线层的布线层。

公开(公告)号：US08222529B2

公开(公告)日：2012-07-17

申请号：US12588502

申请日：2009-10-16

Applicant: Je Hong Sung ,  Jin Waun Kim ,  Myung Whun Chang

Inventor： Je Hong Sung ,  Jin Waun Kim ,  Myung Whun Chang

IPC: H05K1/03

CPC classification number: H05K3/4061 ,  H05K1/113 ,  H05K3/0029 ,  H05K3/245 ,  H05K3/4629 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2203/0242 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention provides a ceramic substrate including: a ceramic stacked layer structure in which multiple ceramic layers are stacked to be interconnected through a via provided within each of the ceramic layers, the ceramic stacked layer structure having a hole provided therein to expose a top portion of the via provided within a ceramic layer of being a surface layer; a conductive material filled within the hole; and an external electrode formed on the surface of the ceramic stacked layer structure so that the external electrode is electrically connected to the conductive material, and a manufacturing method thereof.

Abstract translation: 本发明提供一种陶瓷基板，其特征在于，包括：陶瓷层叠体，其中多个陶瓷层通过设置在各陶瓷层内的通孔进行层叠而互连，所述陶瓷层叠体结构具有设置在其内的孔， 位于作为表层的陶瓷层内的通孔; 填充在孔内的导电材料; 以及外部电极，其形成在陶瓷层叠结构的表面上，使得外部电极与导电材料电连接，及其制造方法。

公开(公告)号：US08221132B2

公开(公告)日：2012-07-17

申请号：US12868370

申请日：2010-08-25

Applicant: Myoungsoo Jeon ,  Attalee Snarr Taylor ,  John Joseph Consoli

Inventor： Myoungsoo Jeon ,  Attalee Snarr Taylor ,  John Joseph Consoli

IPC: H01R12/00

CPC classification number: H05K3/308 ,  H01R12/585 ,  H05K1/116 ,  H05K3/366 ,  H05K2201/044 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: An electrical connector assembly includes a circuit board and an electrical connector mounted on the circuit board. The circuit board has a circuit board body having first and second surfaces and through-holes bored between the first and second surfaces. The circuit board has signal traces on internal layers of the circuit board that are generally parallel to the first and second surfaces. Portions of the circuit board body within the through-holes are etched away to expose portions of the signal traces beyond the circuit board body within the corresponding through-hole. The electrical connector includes a housing and signal terminals held by the housing. The signal terminals are received in respective through-holes of the circuit board and engage the corresponding signal traces.

Abstract translation: 电连接器组件包括电路板和安装在电路板上的电连接器。 电路板具有电路板主体，其具有在第一表面和第二表面之间钻孔的第一表面和第二表面以及通孔。 电路板在电路板的内层上具有通常平行于第一和第二表面的信号迹线。 蚀刻掉通孔内的电路板主体的部分，以将信号迹线的部分暴露在对应的通孔内的电路板主体之外。 电连接器包括壳体和由壳体保持的信号端子。 信号端子被接收在电路板的相应通孔中并与相应的信号迹线接合。

公开(公告)号：US20120175643A1

公开(公告)日：2012-07-12

申请号：US12987148

申请日：2011-01-09

Applicant: R. SCOTT WEST

Inventor： R. SCOTT WEST

IPC: H01L33/62 ,  H01L21/60 ,  H01L33/00 ,  H01L33/08

CPC classification number: H01L33/62 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/644 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2933/0066 ,  H05K1/021 ,  H05K3/0061 ,  H05K2201/09145 ,  H05K2201/09845 ,  H05K2201/10106 ,  H05K2201/10409 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.

Abstract translation: 标准化的光子构建块用于制造分立的发光体以及阵列产品。 每个光子构建块具有安装在基板上的一个或多个LED芯片。 没有电导体通过衬底的顶表面和底表面之间。 光子构建块由连接到散热器的互连结构支撑。 每个光子构建块的衬底的顶表面上的着陆焊盘附接到布置在互连结构的唇缘的下侧上的接触焊盘。 在焊料回流工艺中，光子构建块在互连结构内自对准。 互连结构上的导体通过接触焊盘和着陆焊盘电耦合到光子构建块中的LED管芯。 互连结构的底表面与光子积木的基底的底表面共面。

公开(公告)号：US20120153463A1

公开(公告)日：2012-06-21

申请号：US13324535

申请日：2011-12-13

Applicant: Shinnosuke MAEDA

Inventor： Shinnosuke MAEDA

IPC: H01L23/498 ,  H05K1/00 ,  H05K3/10 ,  H05K1/11

CPC classification number: H01L23/5226 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.

Abstract translation: 为了提供通孔导体的连接可靠性提高的多层布线基板，在将下导体层与上导体层隔离的树脂层间绝缘层中形成通孔，并且通孔形成在用于连接的通孔中 下导体层和上导体层。 树脂层间绝缘层的表面是粗糙表面，并且通孔在树脂层间绝缘层的粗糙表面开口。 步进部分形成在通孔周围的打开边缘区域中，使得阶梯部分从围绕开口边缘区域的周边区域凹陷。 阶梯部分的表面粗糙度高于外围区域。

公开(公告)号：US08201328B2

公开(公告)日：2012-06-19

申请号：US12315811

申请日：2008-12-04

Applicant: Roya Yaghmai ,  Frank B. Parrish ,  Daniel DeLessert

Inventor： Roya Yaghmai ,  Frank B. Parrish ,  Daniel DeLessert

IPC: H01K3/10 ,  H05K3/26 ,  H05K3/10

CPC classification number: H05K1/0243 ,  G01R31/2889 ,  H05K3/3405 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/09845 ,  H05K2201/10356 ,  H05K2201/10446 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In one implementation, a method is provided for constructing an interface module which includes constructing a board having a signal via through the board, and having at least one ground via extending through the board. The method further includes back drilling the signal via to create a center conductor hole above a remaining portion of the signal via and back drilling a shield opening in the board and at least part way into the at least one ground via such that a height of the center conductor hole is reduced. The method further includes plating the shield opening and the center conductor hole, and back drilling to remove a portion of the plating to electrically isolate the plated shield opening and the plated center conductor hole.

Abstract translation: 在一个实现中，提供了一种用于构建接口模块的方法，该接口模块包括通过板构建具有信号通孔的板，并且通过板延伸至少一个接地。 该方法还包括：背面钻孔信号通道，以在信号通道的剩余部分上方形成中心导体孔，并且在该板的后面钻出屏蔽开口，并且至少部分地进入至少一个地面，使得 中心导体孔减少。 该方法还包括对屏蔽开口和中心导体孔进行电镀，并进行背面钻孔以去除电镀部分以电隔离电镀屏蔽开口和电镀中心导体孔。

公开(公告)号：US20120145445A1

公开(公告)日：2012-06-14

申请号：US13403042

申请日：2012-02-23

Applicant: Masashi ARAI ,  Mayuko NISHIHARA

Inventor： Masashi ARAI ,  Mayuko NISHIHARA

IPC: H05K1/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/09481 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10636 ,  H05K2203/0191 ,  Y02P70/611 ,  Y10T29/4916

Abstract: A resin multilayer substrate includes a component-containing layer and a thin resin layer stacked on a surface of the component-containing layer. The resin multilayer substrate further includes a surface electrode located on a surface opposite to the surface of the thin resin layer stacked on the component-containing layer, a first via conductor provided in the component-containing layer, which includes an end reaching one surface of the component-containing layer, and a second via conductor provided in the thin resin layer, which includes a first end electrically connected to the surface electrode and a second end electrically connected to the via conductor. A portion of the thin resin layer in contact with the second via conductor defines a projection projecting into the first via conductor.

Abstract translation: 树脂多层基板包括层叠在含有成分层的表面上的成分含有层和薄树脂层。 树脂多层基板还包括位于与层叠在含有成分层的薄树脂层的表面相反的表面上的表面电极，设置在含有成分的层中的第一通孔导体， 所述部件含有层和设置在所述薄树脂层中的第二通路导体，所述第二通路导体包括电连接到所述表面电极的第一端和与所述通孔导体电连接的第二端。 与第二通孔导体接触的薄树脂层的一部分限定突出到第一通孔导体中的突起。

公开(公告)号：US20120132463A1

公开(公告)日：2012-05-31

申请号：US13365616

申请日：2012-02-03

Applicant: Hiroyuki Mori ,  Kazushige Kawasaki

Inventor： Hiroyuki Mori ,  Kazushige Kawasaki

IPC: H05K1/18 ,  H01L21/50 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/205 ,  H05K3/421 ,  H05K3/4682 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/0574 ,  Y10T29/49124 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter is larger than that of a contact portion. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Diameter of the contact portion is substantially the same as diameter of an under bump metal at the semiconductor chip side, when mechanical stress is applied, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.

Abstract translation: 本发明的实施例提供了一种印刷线路板，其中安装的半导体芯片的焊料凸块不容易破裂。 印刷电路板包括具有主表面的电介质层和嵌入电介质层中的连接焊盘。 连接垫的形状像一顶帽子。 也就是说，连接焊盘包括其直径大于接触部分的直径的板部分。 接触部分的主表面在电介质层的主表面露出。 接触部的直径与半导体芯片侧的凸块状金属的直径基本相同，当施加机械应力时，应力均匀地分散到连接焊盘和下凸块金属两者上，因此破裂不容易 发生。