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    ACTIVE FET BODY DEVICE AND MANUFACTURE THEREFOR
    1.
    发明专利
    ACTIVE FET BODY DEVICE AND MANUFACTURE THEREFOR 失效

    公开(公告)号：JP2000058861A

    公开(公告)日：2000-02-25

    申请号：JP22482799

    申请日：1999-08-09

    Applicant: IBM

    Inventor： ASSADERAGHI FARIBORZ ,  BERTIN CLAUDE L ,  GAMBINO JEFFREY P ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To obtain an active FET body device capable of balancing high-speed electric charges, decreasing off-current, and increasing on-current. SOLUTION: This embodiment comprises a silicon substrate 2, a silicon dioxide layer 3, a monocrystal silicon layer 4, a silicon dioxide layer 5, a spacer 13 of N+ doped polysilicon, a conformal layer 15 of a conductive diffusion preventing substance, a metal silicide layer 16, a CVD silicon dioxide layer 17, an insulator spacer 18, a silicon oxide layer 19, and a polysilicon 21. In an off-state, a gate contact with a body holds the body at a low word line level. In this state, a threshold takes a larger value. In addition to a voltage added to the N+ part 13 of a gate conductor, a potential from the body to a source rises. As a result, if the device is turned on, Vt lowers. By the effects of a dynamic Vt fall accompanied by a low off-current, this embodiment is suitable for a device using a very low voltage.

    HIGH PERFORMANCE AND HIGH BAND WIDTH MEMORY USING SDRAM AND SYSTEM THEREFOR
    3.
    发明专利
    HIGH PERFORMANCE AND HIGH BAND WIDTH MEMORY USING SDRAM AND SYSTEM THEREFOR 失效

    公开(公告)号：JPH10340224A

    公开(公告)日：1998-12-22

    申请号：JP13174498

    申请日：1998-05-14

    Applicant: IBM

    Inventor： BERTIN CLAUDE L ,  ERIC L HEDBERG

    IPC: G11C11/407 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401

    Abstract: PROBLEM TO BE SOLVED: To provide a high performance/high band width RAM bus architecture that reduces the waiting time through the use of standard synchronous DRAM (SDRAM) chips. SOLUTION: The high performance/high band width memory bus architecture and module contain the standard synchronous DRAM(SDRAM) chips 12, and reduce the waiting time and the number of pins. Four bus pins detach an input command from data and establish a parallel system operation. An independent memory operation can be improved compared to a regular SDRAM operation by maintaining a 'packet'-type transaction. In the architecture, the bus is divided into command input and data input, which are detached from output data.

    DYNAMIC RANDOM ACCESS MEMORY
    4.
    发明专利
    DYNAMIC RANDOM ACCESS MEMORY 失效

    公开(公告)号：JPH10283797A

    公开(公告)日：1998-10-23

    申请号：JP8835198

    申请日：1998-04-01

    Applicant: IBM

    Inventor： MARK W KELLOGG ,  TIMOTHY J DILL ,  ERIC L HEDBERG ,  BERTIN CLAUDE L

    IPC: G06F12/16 ,  G06F11/10 ,  G11C7/10 ,  G11C11/401 ,  G11C29/42 ,  G11C29/00

    Abstract: PROBLEM TO BE SOLVED: To provide a high-band DRAM which can be used for an error detecting application. SOLUTION: A DRAM array 140 is divided into two or more subarrays 142, 144, 146, and 148. The subarrays are arranged in addressable lines and rows. When the DRAMs are programmed in a normal mode, the burst length becomes '8' and all address spaces of the DRAMs can be utilized for data storage. When the DRAMs are programmed for error detection (ECC mode), the burst length becomes '9' and the array is reconstituted at the part of the array which gives the ninth byte. The address spaces of the DRAMs are reduced by 1/8 in the ECC mode. It is preferable that all nine locations exist on the same page. Each page is divided into eight equal parts. In the normal mode, all of, the eight parts are assigned to the storage of data and, in the FCC mode, seven of the eights parts are assigned to the storage of data and the remaining one part is assigned to the storage of check bits.

    GAIN MEMORY CELL CIRCUIT
    5.
    发明专利
    GAIN MEMORY CELL CIRCUIT 失效

    公开(公告)号：JPH10241358A

    公开(公告)日：1998-09-11

    申请号：JP2699798

    申请日：1998-02-09

    Applicant: IBM

    Inventor： HOUGHTON RUSSELL J ,  BERTIN CLAUDE L ,  FIFIELD JOHN A ,  MILLER CHRISTOPHER P ,  TONTI WILLIAM R

    IPC: G11C11/402 ,  G11C11/403 ,  G11C11/405

    Abstract: PROBLEM TO BE SOLVED: To prevent read-out disturbance from an unselected cell by reading out a written word value stored on a storage node by means of a read transistor via a diode between bit lines. SOLUTION: When a write transistor Tw0 in a gain cell 20 is operated by a write-in word line WLW0, a value of a write-in bit line BLW0 is stored on the storage node SN0. When a read-out word line WLR0 is enabled to work, the read transistor Tr0 to be connected with the storage node SN0 in this case is connected via the diode D0 to a read-out bit line BLR0, so as to read out the stored value. The diode D0 is capable of preventing conductivity in the reverse direction of the read transistor Tr0, thus preventing disturbance from another cell, and also decreasing capacitance of the bit line. The same is the case with the other memory cells.

    HIGH-INTEGRATION CHIP-ON-CHIP PACKAGING
    7.
    发明专利
    HIGH-INTEGRATION CHIP-ON-CHIP PACKAGING 失效

    公开(公告)号：JP2000156461A

    公开(公告)日：2000-06-06

    申请号：JP15140999

    申请日：1999-05-31

    Applicant: IBM

    Inventor： BERTIN CLAUDE L ,  FERENCE THOMAS GEORGE ,  WAYNE JOHN HOWEL ,  SPROGIS EDMUND J

    IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

    Abstract: PROBLEM TO BE SOLVED: To individually set a chip and to achieve a compact semiconductor package with a high-integration technique by equipping a plurality of independent chips that are electrically connected and function completely and chip-on- chip part connection/interconnection for electrically connecting the chips to an external circuit. SOLUTION: Chip-on-chip parts 10 include a first chip 30, a second chip 40, and chip-on-chip part connection 20. An active region 35 of the first chip 30 is electrically connected to an active region 45 of the second chip 40 via solder ball connection 50 or electrical connection between chips. Also, the chip- on-chip part connection 20 is a solder column 22 that is connected to the first chip 30, and the solder column 22 can connect the chip-on-chip parts 10 to an external circuit via a substrate, thus achieving a reliable, compact semiconductor package with high-integration technique and at the same time improving thermal performance.

    REFERENCE POTENTIAL SENSING DATA WITHIN ELECTRONIC STORAGE ELEMENT
    8.
    发明专利
    REFERENCE POTENTIAL SENSING DATA WITHIN ELECTRONIC STORAGE ELEMENT 失效

    公开(公告)号：JPH1173766A

    公开(公告)日：1999-03-16

    申请号：JP16885898

    申请日：1998-06-16

    Applicant: IBM

    Inventor： BERTIN CLAUDE L ,  JOHN ATKINSON FIFIEL ,  RUSSELL JAMES HORTON ,  MILLER CHRISTOPHER P ,  WILLIAM ROBERT PATRICK TONTY

    IPC: G11C11/401 ,  G11C7/14

    Abstract: PROBLEM TO BE SOLVED: To improve sense characteristics of a IC memory. SOLUTION: Two bit lines whose respective bit lines have a right half and left half and plural similar memory cells connected to respective halves of respective bit lines are included in a column of an integrated memory circuit. One of memory cells connected to respective lines is used as a reference and the other cells are used for data storage. Respective halves of respective bit lines are connected to a sense node of a sense amplifier latch via independently controlled transistor switches SW1-SW4. The switch SW1 is turned on and the SW2 is turned off in order to read data from a first half of a first bit line 204. Respective switches SW3, SW4 of a second bit line 206 are turned on. Nearly same effective loads are provided in respective halves of respective bit lines 204-206. Therefore, the load applied to a first sense node 214 is the nearly half of the load applied to a second sense mode 224. The output of a memory element is selected so that a reference potential becomes the nearly middle of the potential in the half of the bit line connected to the memory element storing a high value and low value.

    10.
    发明专利
    未知

    公开(公告)号：IT7925852D0

    公开(公告)日：1979-09-20

    申请号：IT2585279

    申请日：1979-09-20

    Applicant: IBM

    Inventor： BULA JOHN ,  BERTIN CLAUDE L ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

    IPC: G11C17/12 ,  G11C17/00 ,  H01L23/525 ,  G11C

    Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

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