公开(公告)号：AU1330897A

公开(公告)日：1998-07-15

申请号：AU1330897

申请日：1996-12-16

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA JEAN ,  UZOH CYPRIAN EMEKA ,  WONG KWONG HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFERY LOUIS

IPC: C25D7/12 ,  H01L21/28 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches.

公开(公告)号：DE3477868D1

公开(公告)日：1989-05-24

申请号：DE3477868

申请日：1984-06-20

Applicant: IBM

Inventor： ACOSTA RAUL EDMUNDO ,  HORKANS WILMA JEAN ,  MUKHERJEE RUBY ,  OLSEN JUDITH DIANE

IPC: H05K1/09 ,  C23C30/00 ,  H01L21/28 ,  H01L29/43 ,  H05K3/24 ,  H05K3/28 ,  H05K3/38 ,  H05K3/46

公开(公告)号：IE79088B1

公开(公告)日：1998-04-08

申请号：IE960846

申请日：1996-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DATTA MADAV ,  DELIGIANNI HARIKLIA ,  HORKANS WILMA JEAN ,  KANG SUNG KWON ,  KWIETNIAK KEITH THOMAS ,  MATHAD GANGADHARA SWAMI ,  PURUSHOTHAMAN SAMPATH ,  SHI LEATHEN ,  TONG HO-MING

IPC: B23K35/26 ,  B23K35/00 ,  B32B15/01 ,  C22C13/00 ,  C22C13/02 ,  H01L21/60 ,  H01L23/485 ,  H01L23/488

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

公开(公告)号：IE960846A1

公开(公告)日：1997-09-24

申请号：IE960846

申请日：1996-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DATTA MADAV ,  DELIGIANNI HARIKLIA ,  HORKANS WILMA JEAN ,  KANG SUNG KWON ,  KWIETNIAK KEITH THOMAS ,  MATHAD GANGADHARA SWAMI ,  PURUSHOTHAMAN SAMPATH ,  SHI LEATHEN ,  TONG HO-MING

IPC: B23K35/26 ,  B23K35/00 ,  B32B15/01 ,  C22C13/00 ,  C22C13/02 ,  H01L21/60 ,  H01L23/485 ,  H01L23/488

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe, and NiCoFe on the adhesion/barrier layer, and lead free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.