公开(公告)号：EP2313921A4

公开(公告)日：2014-08-27

申请号：EP09805365

申请日：2009-07-28

Applicant: IBM

Inventor： COLLINS DAVID S ,  JOSEPH ALVIN ,  LINDGREN PETER J ,  STAMPER ANTHONY K ,  WATSON KIMBALL M

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

公开(公告)号：EP2313919A4

公开(公告)日：2014-01-15

申请号：EP09805345

申请日：2009-07-22

Applicant: IBM

Inventor： DING HANYI ,  JOSEPH ALVIN ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/481 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/0405 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01068 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：GB2506816A

公开(公告)日：2014-04-09

申请号：GB201401778

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN ,  KHATER MARWAN ,  LIU QIZHI

IPC: H01L21/8249 ,  H01L29/732

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

公开(公告)号：GB2487860B

公开(公告)日：2014-08-27

申请号：GB201206521

申请日：2010-09-30

Applicant: IBM

Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN ,  JOSEPH ALVIN ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

IPC: H01L27/12

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

公开(公告)号：GB2495464A

公开(公告)日：2013-04-10

申请号：GB201302640

申请日：2011-07-28

Applicant: IBM

Inventor： BOTULA ALAN B ,  JOSEPH ALVIN ,  SLINKMAN JAMES A ,  WOLF RANDY LEE

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12

Abstract: A method, integrated circuit and design structure includes a silicon substrate layer (102) having trench structures (106) and an ion impurity implant (108). An insulator layer (110) is positioned on and contacts the silicon substrate layer. The insulator layer (110) fills the trench structures (106). A circuitry layer is positioned on and contacts the buried insulator layer (110). The circuitry layer comprises groups of active circuits (112) separated by passive structures (114). The trench structures (106) are positioned between the groups of active circuits (112) when the integrated circuit structure is viewed from the top view. Thus, the trench structures (106) are below the passive structures (114) and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

公开(公告)号：GB2494358A

公开(公告)日：2013-03-06

申请号：GB201300063

申请日：2011-05-17

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed are embodiments of an improved transistor structure (100) (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure (100). The structure embodiments can incorporate a dielectric layer (130) sandwiched between an intrinsic base layer (120) and a raised extrinsic base layer (140) to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap (150) for an intrinsic base layer (120) to extrinsic base layer (140) link-up region to reduce base resistance Rb and a dielectric spacer (160) between the extrinsic base layer (140) and an emitter layer (180) to reduce base- emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer (130), the width of the conductive strap (150), the width of the dielectric spacer (160) and the width of the emitter layer (180)) to be selectively adjusted in order to optimize transistor performance.

公开(公告)号：GB2495464B

公开(公告)日：2013-09-04

申请号：GB201302640

申请日：2011-07-28

Applicant: IBM

Inventor： BOTULA ALAN B ,  JOSEPH ALVIN ,  SLINKMAN JAMES A ,  WOLF RANDY LEE

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12

公开(公告)号：GB2487860A

公开(公告)日：2012-08-08

申请号：GB201206521

申请日：2010-09-30

Applicant: IBM

Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN ,  JOSEPH ALVIN ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

IPC: H01L27/12

Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

公开(公告)号：GB2494358B

公开(公告)日：2014-04-16

申请号：GB201300063

申请日：2011-05-17

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

公开(公告)号：GB2485718B

公开(公告)日：2013-10-16

申请号：GB201203499

申请日：2010-08-12

Applicant: IBM

Inventor： DING HANYI ,  JOSEPH ALVIN ,  WOODS WAYNE H

IPC: H01P5/16 ,  H01L23/48 ,  H01P11/00