-
1.
公开(公告)号:JP2003218177A
公开(公告)日:2003-07-31
申请号:JP2003008636
申请日:2003-01-16
Applicant: IBM
Inventor: MAGERLEIN JOHN HAROLD , MCKNIGHT SAMUEL ROY , PETRARCA KEVIN SHAWN , PURUSHOTHAMAN SAMPATH , SAMBUCETTI CARLOS JUAN , VAN HORN JOSEPH J , VOLANT RICHARD PAUL , WALKER GEORGE FREDERICK
Abstract: PROBLEM TO BE SOLVED: To provide an ability to test and 'burn in' device chips that require ultra high pitch I/O pads. SOLUTION: A system for testing a collection of the device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; the carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable. COPYRIGHT: (C)2003,JPO
-
公开(公告)号:JP2003273158A
公开(公告)日:2003-09-26
申请号:JP2003003619
申请日:2003-01-09
Inventor: FURMAN BRUCE KENNETH , SURENDRA MAHESWARAN , GOMA SHERIF A , KARECKI ANNA , KARECKI SIMON M , MAGERLEIN JOHN HAROLD , PETRARCA KEVIN SHAWN , PURUSHOTHAMAN SAMPATH , SAMBUCETTI CARLOS JUAN , VOLANT RICHARD PAUL , WALKER GEORGE FREDERICK
IPC: H01L23/52 , H01L21/288 , H01L21/3205 , H01L21/60 , H05K1/03 , H05K1/11 , H05K3/38
CPC classification number: H01L24/12 , H01L21/288 , H01L21/2885 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05571 , H01L2224/05599 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/13582 , H01L2224/13616 , H01L2224/13644 , H01L2224/13655 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H05K2201/10674 , H01L2224/45111 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
Abstract: PROBLEM TO BE SOLVED: To provide a system making an interconnection with a quite high density by connecting device chips and a chip carrier by using a microjoint interconnect structure.
SOLUTION: In the system, a pair of device chips is mounted on a microjoint interconnect chip carrier by using a microjoint interconnect structure. The microjoint interconnect chip carrier comprises a multilayer substrate having a plurality of receptacles on its surface. A pair of microjoint interconnect pads corresponding to the receptacles is provided on the device chips. Interconnecting wiring enabling an interconnection between the device chips is provided between the receptacles.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题:通过使用微型连接互连结构,通过连接器件芯片和芯片载体来提供使密度相当高的互连的系统。 解决方案:在系统中,通过使用微型连接互连结构将一对器件芯片安装在微型连接互连芯片载体上。 微型连接互连芯片载体包括其表面上具有多个插座的多层基板。 在器件芯片上设置一对对应于插座的微接点互连焊盘。 在插座之间设置能够实现器件芯片之间的互连的互连布线。 版权所有(C)2003,JPO
-
3.
公开(公告)号:AU2002363902A8
公开(公告)日:2003-07-30
申请号:AU2002363902
申请日:2002-12-19
Applicant: IBM
Inventor: PETRARCA KEVIN SHAWN , SAMBUCETTI CARLOS JUAN , PURUSHOTHAMAN SAMPATH , VOLANT RICHARD PAUL , MAGERLEIN JOHN HAROLD , WALKER GEORGE FREDERICK
IPC: H01L21/60 , H01L21/00 , H01L23/485 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/34 , H05K3/38
Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
-
公开(公告)号:DE3570701D1
公开(公告)日:1989-07-06
申请号:DE3570701
申请日:1985-03-07
Applicant: IBM
Inventor: ALPAUGH WARREN ALAN , AMELIO WILLIAM JOSEPH , MARKOVICH VOYA , SAMBUCETTI CARLOS JUAN
Abstract: @ copper is plated onto a dielectric substrate by plating a first layer of copper onto the substrate from an electroless plating bath and plating a second layer of copper onto the first layer of copper from a second and different electroless plating bath. The first and second plating baths differ from each other in at least the cyanide content and oxygen content. The process reduces plating void defects and reduces nodule formation.
-
公开(公告)号:DE3663151D1
公开(公告)日:1989-06-08
申请号:DE3663151
申请日:1986-02-07
Applicant: IBM
Inventor: AMELIO WILLIAM JOSEPH , JUNG DAE YOUNG , MARKOVICH VOYA , SAMBUCETTI CARLOS JUAN
Abstract: A concentrate of a palladium-tin colloidal catalyst is obtained by dissolving stannous chloride in HCI, diluting the solution with HCI and then further diluting the solution with deionized water to thereby obtain a diluted stannous chloride solution. This solution is cooled to room temperature or below. A palladium chloride solution is obtained by dissolving palladium chloride in HCI which in tum is also cooled to room temperature or below. The palladium chloride solution is gradually added to the stannous chloride solution and mixed at about room temperature in order to obtain a homogeneous solution. The temperature of the solution is then gradually increased to about 105°C to about 110°C and maintained at that temperature for sufficient time to obtain a homogeneous solution of substantially uniform colloidal particles. The solution of colloidal particles is slowly cooled to about room temperature. The palladium-tin colloidal system is produced reproducibly and is applicable in the manufacturing of highly complex circuitry.
-
公开(公告)号:DE2808144A1
公开(公告)日:1978-09-07
申请号:DE2808144
申请日:1978-02-25
Applicant: IBM
Inventor: KOVAC ZLATA , SAMBUCETTI CARLOS JUAN
Abstract: Water based magnetic colloidal fluids, useable as inks, when prepared by coating chemically precipitated magnetite (Fe3O4) with an adsorption site providing coating agent including certain organic anions, such as sulfates, sulfonates or amino carboxilates, and then dispersing the coated product with non-ionic, anionic or cationic surfactants may exhibit selectably cationic, anionic or non-ionic charge responsiveness.
-
公开(公告)号:SG72751A1
公开(公告)日:2000-05-23
申请号:SG1997002768
申请日:1997-08-02
Applicant: IBM
Inventor: BROUILLETTE GUY PAUL , DANOVITCH DAVID HIRSCH , LIEHR MICHAEL , MOTSIFF WILLIAM THOMAS , ROLDAN JUDITH MARIE , SAMBUCETTI CARLOS JUAN , SARAF RAVI F
Abstract: An interconnect system that has low alpha particle emission characteristics for use in an electronic device includes a semiconductor chip that has an upper surface and spaced apart electrically resistive bumps positioned on conductive regions of the upper surface, the electrically resistive bumps are made of a composite material of a polymer and metal particles, and a substrate that has conductive regions bonded to the electrically resistive bumps in a bonding process wherein the electrically resistive bumps convert to electrically conductive bumps after the bonding process.
-
公开(公告)号:DE3480857D1
公开(公告)日:1990-02-01
申请号:DE3480857
申请日:1984-10-09
Applicant: IBM
Inventor: AMELIO WILLIAM JOSEPH , LEMON GARY KEVIN , MARKOVICH VOYA , PANASIK THEODORE , SAMBUCETTI CARLOS JUAN , TREVITT DONNA JEAN
Abstract: Multistep process for electroless plating copper onto a non-conductive surface including the steps of 1) laminating a rough copper sheet onto the non-conductive surface; 2) etching away all the copper; 31 conditioning the surface with multifunctional positively charged molecules derived from copolymers of polyacrylamide and functionally active tetraalkylammonium compounds in an diluted inorganic acid; 4) activating the conditioned surface preferably with stannous palladium chloride particles; 5) treating the activated surface with deionized water and diluted HCI; 6) applying a photoresist layer to the surface and selectively exposing and developing the photoresist to produce a mask corresponding to the negative of the desired circuit pattern; and 7) plating copper using successively two baths differing in their oxygen and CN - concentration, where the foregoing steps are interspersed with washing steps.The inventive method is particularly useful to produce copper circuit on substrates of glass, thermoplastics and thermosetting resins, like epoxy cards and boards. If the step 1) is omitted the method is also applicable in reworking substrates having already undergone copper plating and having been rejected due to failures.
-
公开(公告)号:DE2623508A1
公开(公告)日:1976-12-23
申请号:DE2623508
申请日:1976-05-26
Applicant: IBM
Inventor: SAMBUCETTI CARLOS JUAN , MITCHELL JOSEPH WILLIAM
Abstract: Improvements in water based magnetic inks of the type containing non-ionic, cationic and/or anionic surfactants by the inclusion of glycerol, non-volatile solvent such as mono-lower alkyl ethers of ethylene glycol and low molecular weight polyethylene diols.
-
10.
公开(公告)号:AU2002363902A1
公开(公告)日:2003-07-30
申请号:AU2002363902
申请日:2002-12-19
Applicant: IBM
Inventor: MAGERLEIN JOHN HAROLD , PETRARCA KEVIN SHAWN , PURUSHOTHAMAN SAMPATH , SAMBUCETTI CARLOS JUAN , VOLANT RICHARD PAUL , WALKER GEORGE FREDERICK
IPC: H01L21/60 , H01L21/00 , H01L23/485 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/34 , H05K3/38
Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
-
-
-
-
-
-
-
-
-