公开(公告)号：JP2003199129A

公开(公告)日：2003-07-11

申请号：JP2002338803

申请日：2002-11-22

Applicant: ST MICROELECTRONICS SRL

Inventor： LARI FERDINANDO ,  DEVECCHI DANIELE ,  VIZZI EMANUELA

IPC: H04Q3/42 ,  H04M3/00 ,  H04M19/00

Abstract: PROBLEM TO BE SOLVED: To provide a line interface (30) operated at a low feed voltage that couples a broadband XDSL signal and a voice band telephone signal on a twisted-pair copper line. SOLUTION: In the line interface (30) where the voice-band signal carries a DC feed for a user telephone and also a voice signal, a ring signal, the XDSL signal, and the voice signal are coupled to at least one primary winding of a line transformer, and at least a secondary winding (40) pilots a twisted-pair telephone line (41), the secondary winding (40) is DC-coupled with the line (41) and the ring and feed signals are injected into the telephone line (41) by a circuit (43) arranged in parallel with the secondary winding (40). COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003163294A

公开(公告)日：2003-06-06

申请号：JP2002294069

申请日：2002-10-07

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPRARA PAOLO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To simplify the step of manufacturing a double charge storage location memory cell. SOLUTION: A dielectric stack 120 is disposed over the entire upper side surface of a structure. A contact opening 121 is formed in the dielectric layer 120 lowered to the surface of a bit line diffused part 115 of the specified region at the outside of the memory cell sub-array. Metal bit lines 123A, 123B are specified to cross a word line 119 on the bit line diffused part 115 so as to bring into contact with the position corresponding to the specified region by a normal contact forming technique and a metallization technique. The metal bit line restricts the voltage drop along the bit line diffused part 115. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003152160A

公开(公告)日：2003-05-23

申请号：JP2002316673

申请日：2002-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  PINTO ANTONIO ,  MAGLI ANGELO

IPC: H01L25/07 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/18 ,  H01L29/417

Abstract: PROBLEM TO BE SOLVED: To improve electric connection between an electronic power device and a package and avoid the formation of an uncontrollable chemical composition area. SOLUTION: The electronic power device (1) having an improved structure is manufactured by employing MOS technique so as to have at least one gate finger area (3) and related source areas (4) positioned at both sides of the area (3). The electronic power device is provided with at least first level metallic layers (3', 4') arranged so as to be contacted individually with the gate finger area and the source areas, and a passivation layer (5) for protection which is arranged so as to cover the gate finger area. A wetting metallic layer (7) is advantageous to be built up on the passivation layer and the first level metallic layer (4') for covering the source area. According to this method, an additional wetting metallic layer functions as a second level metallic layer.

公开(公告)号：JP2003123486A

公开(公告)日：2003-04-25

申请号：JP2002287067

申请日：2002-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: G11C16/02 ,  G11C11/56 ,  G11C19/28

Abstract: PROBLEM TO BE SOLVED: To enable increasing capacity of a storage device of a nonvolatile memory. SOLUTION: In a programming method of a multi-level, each memory region can be programmed by non-binary-number of a level, and integer of bits, for example 5, is stored in an adjacent memory region. Therefore, bits to be stored in two memory regions are divided into two sets, a first set prescribes a level of binary number being higher than a level of non-binary number. When the first set written during programming corresponds to a level being lower than a level of non-binary number, the first set is written in the first region and the second set is written in the second region (33, 34). When it is higher than non-binary number of a level, the first set is written in the second region and the second set is written in the first region (35, 36). The first set written in the second region is stored with a level being different from the second set. Consequently, writing of a level stored in the first set is confirmed, and bits read out from two regions are almost related to bits of two sets.

公开(公告)号：JP2002202320A

公开(公告)日：2002-07-19

申请号：JP2001347845

申请日：2001-11-13

Applicant: ST MICROELECTRONICS SRL

Inventor： CHIESA ENRICO

IPC: G01D3/028 ,  G01D3/06 ,  G01P15/00 ,  G01P15/08 ,  G01P15/125 ,  G01P15/13 ,  G01P21/00

Abstract: PROBLEM TO BE SOLVED: To at least partially overcome a conventional defect. SOLUTION: A sensing device 50' comprises a microelectromechanical structure, and a control loop 53' for controlling the microelectromechanical structure. The microelectromechanical structure comprises a stator element and a rotor element coupled together. The control loop 53' comprises a position interface 56 supplying a position signal VOUT indicative of the position of the rotor element and a one-bit quantizer 66 receiving the position signal VOUT and supplying a corresponding bit sequence OUT. The sensing device 50' comprises calibration devices 84 and 86 for calibrating the microelectromechanical structure and including a microactuator coupled to the rotor element and driving circuits 84 and 86 for driving the microactuator, and receiving the bit sequence OUT and supplying a driving signal VCAL correlated to a mean value MBS of the bit sequencer OUT to the microactuator in a given time window.

公开(公告)号：JP2002050187A

公开(公告)日：2002-02-15

申请号：JP2001207874

申请日：2001-07-09

Applicant: ST MICROELECTRONICS SRL

Inventor： VISCONTI ANGELO

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34

Abstract: PROBLEM TO BE SOLVED: To provide a method for changing threshold voltage of a non-volatile memory cells at high speed and the circuit configuration that optimizes the uses of a charge pump and the device reliability. SOLUTION: This method is a method for changing threshold voltage of plural non-volatile memory cells after erasure processing, for example, flash EEPROM memory cells (NOR-MX). This method is characterized in that it is provided with a step in which all column lines are connected to a voltage supply source (CH-P, V-REG) to optimize use of a voltage source for column bias while equalization of threshold voltage is performed at high speed, a step (V-SEN) in which supply voltage is monitored, and a step (V-GEN, R-REG) in which voltage being variable from the prescribed minimum value to the prescribed maximum value and its change rate is adjusted to the maximum possible value being compatible with a state, in which supply voltage of a column line is kept to the approximately fixed prescribed value, is supplied to all row lines.

公开(公告)号：JP2001346770A

公开(公告)日：2001-12-18

申请号：JP2001106147

申请日：2001-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMA GIUSEPPE ,  AVELLA LEONARDO DINO ,  CUCE ANTONINO ,  PLATANIA DAVIDE

IPC: A61B5/022

Abstract: PROBLEM TO BE SOLVED: To provide a sphygmomanometer of high reliability capable of automatically controlling measuring action. SOLUTION: A sphygmomanometer to take the maximum value and the minimum value of artery pressure, and record them is provided, and it is provided with a motion detecting and sorting means to generate an index for a current physical effort state that coincides with the indicated minimum and the maximum artery pressures, and a blood pressure control means to control execution of fuzzy logic processes for functions of the sphygmomanometer and the indicated values. A sensor for expansion of inner air pressure of an air compressing sleeve installed on an arm of a subject is used for detecting motion of the arm, and at least one second sensor for motion is fixed to the chest of the subject to be used.

公开(公告)号：JP2001313374A

公开(公告)日：2001-11-09

申请号：JP2001095119

申请日：2001-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PESCHIAROLI DANIELA ,  MAURELLI ALFONSO ,  PALUMBO ELISABETTA ,  PIAZZA FAUSTO

IPC: H01L21/8238 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for integrating a nonvolatile memory and a high performance logic circuit network in the same semiconductor chip. SOLUTION: The floating gate of a memory cell of a nonvolatile memory and a gate electrode of a high voltage transistor regarding the nonvolatile memory are formed of a first polysilicon layer, and the control gate of a memory cell of the nonvolatile memory and the gate electrode of a low voltage transistor regarding a high performance logic circuit network are formed of a second polysilicon layer.

公开(公告)号：JP2001291049A

公开(公告)日：2001-10-19

申请号：JP2001052695

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  CAZZANIGA MARCO ,  VENCA ALESSANDRO

IPC: G06G7/16 ,  G06G7/163 ,  H03D7/14

Abstract: PROBLEM TO BE SOLVED: To provide a low supply voltage analog multiplier for supplying an extremely low supply voltage and improving the linearity of input while keeping a sufficient speed by performing the cascade connection of plural stages. SOLUTION: A pair of differential cells 10 and 11 are provided and the respective differential cells are provided with a pair of bipolar transistors 2, 3, 6 and 7 whose emitters are connected to each other. The first transistors 2 and 6 of the respective cells 10 and 11 receive input signals IN+ and IN- at the base terminals and the collector terminals are connected to a first reference voltage Vcc through bias members 4 and 8. The second transistors 3 and 7 of the respective cells are diode constitution and the cells are mutually connected at a common node A corresponding to the base terminals of the second transistors 3 and 7 of the respective pairs.

公开(公告)号：JP2001222430A

公开(公告)日：2001-08-17

申请号：JP2000363469

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： ARENA PAOLO ,  BRANCIFORTE MARCO ,  DI BERNARDO GIOVANNI ,  OCCHIPINTI LUIGI

IPC: G06N3/00 ,  B25J9/16 ,  G05B13/02 ,  G06F9/44 ,  G06N7/02 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To realize an electronic circuit having structural and mechanical features capable of controlling the motion of a multi-actuator electromechanical system. SOLUTION: This electronic circuit relates to a new method for controlling the movement of a multi-architecture electromechanical system having the matrix of locally connected analog sells. Each cell expresses the execution configuration of the hardware of the model of a fuzzy inference rule. It is desired that the model generates and controls the typical reaction diffusion mechanism of autonomous waves by using a fuzzy neural network, and is constituted as a fuzzy circuit architecture to be mounted in the form of an integrated circuit using a VLSICMOS technique. In this fuzzy neural network, a functional relation capable of duplexing a simultaneous reaction diffusion equation is defined, and the state variables of plural cells are processed in a language format by duplexing the simultaneous equation, and the kinetics of a vibration type is applied by two sets of fuzzy rules to be imposed on each cell, and the two dynamic processes are provided with different kinematical characteristics simultaneously.