公开(公告)号：KR1020040038379A

公开(公告)日：2004-05-08

申请号：KR1020020067280

申请日：2002-10-31

Applicant: 한국전자통신연구원

Inventor： 박건식 ,  구진근 ,  박종문 ,  유성욱 ,  윤용선 ,  백규하 ,  김보우

IPC: H01L29/737

Abstract: PURPOSE: A smart power device with a built-in silicon germanium HBT(hetero-junction bipolar transistor) is provided to embody a high voltage tolerance greater than 100 voltage by effectively distributing a drain electric filed, to satisfy an ultra high speed and a high voltage tolerance by using an epi layer of 1.5 micro meter class, and to improve integration by using a trench isolation technology. CONSTITUTION: A substrate(31) is prepared in which an oxygen ion implantation layer with an open space is formed between two semiconductor layers. A silicon germanium HBT is formed on the substrate. A CMOS(complementary metal oxide semiconductor) device is formed on the substrate. A bipolar device is formed on the substrate. An LDMOS(lateral double diffused metal oxide semiconductor) device is formed on the substrate.

Abstract translation: 目的：通过有效分配漏极电场，提供内置硅锗HBT（异质结双极晶体管）的智能功率器件，以实现大于100的高电压容限，以满足超高速和高速 通过使用1.5微米级的外延层进行电压容限，并通过使用沟槽隔离技术改善集成度。 构成：制备其中在两个半导体层之间形成具有开放空间的氧离子注入层的衬底（31）。 在基板上形成硅锗HBT。 在基板上形成CMOS（互补金属氧化物半导体）器件。 在基板上形成双极器件。 在基板上形成LDMOS（横向双扩散金属氧化物半导体）器件。

公开(公告)号：KR1020030056567A

公开(公告)日：2003-07-04

申请号：KR1020010086829

申请日：2001-12-28

Applicant: 한국전자통신연구원

Inventor： 김진규 ,  엄낙웅 ,  김보우

IPC: G06F13/40

Abstract: PURPOSE: A bus architecture for a system chip having a multiprocessor and peripheral blocks is provided to improve the system performance through the extension of a bandwidth and the enhanced entire data processing ratio by separating the data bus between a master and a slave block into a write data bus and a read data bus, and making the master blocks respectively access the slave blocks at the same time. CONSTITUTION: The master blocks(1,2,3) output an address, the write data, and a control signal to the system bus. A bus arbiter(13) processes a request signal outputted from the master blocks(1,2,3). An address decoder(14) decodes the address outputted from the master blocks(1,2,3). The slave blocks(4,5,6) output the data and a response signal after the proper process by receiving the address, the write data, and the control signal outputted from the master blocks(1,2,3). Master multiplexers(7,8,9) output the address, the data, and the control signal of the corresponding master block by receiving a permission signal from the bus arbiter(13). Slave multiplexers(4,5,6) output the data and the response signal of the corresponding slave block by receiving a selection signal from the address decoder(14).

Abstract translation: 目的：提供一种具有多处理器和外设块的系统芯片的总线架构，通过将主器件和从器件之间的数据总线分离成写入，通过扩展带宽和增强的整体数据处理比来提高系统性能 数据总线和读数据总线，并使主机块分别同时访问从模块。 构成：主站（1,2,3）向系统总线输出地址，写入数据和控制信号。 总线仲裁器（13）处理从主块（1,2,3）输出的请求信号。 地址解码器（14）解码从主块（1,2,3）输出的地址。 从块（4,5,6）通过接收从主块（1,2,3）输出的地址，写入数据和控制信号，在正确的处理之后输出数据和响应信号。 主复用器（7,8,9）通过从总线仲裁器（13）接收许可信号来输出相应主机的地址，数据和控制信号。 从复用器（4,5,6）通过从地址解码器（14）接收选择信号来输出相应从属块的数据和响应信号。

公开(公告)号：KR1020030055762A

公开(公告)日：2003-07-04

申请号：KR1020010085840

申请日：2001-12-27

Applicant: 한국전자통신연구원

Inventor： 김명환 ,  엄낙웅 ,  김보우

IPC: G01R31/28

Abstract: PURPOSE: A semiconductor design intellectual property test circuit is provided to test the semiconductor design intellectual property with a data pattern inputted/output directly to an input/output port of the semiconductor design intellectual property. CONSTITUTION: According to the semiconductor design intellectual property test circuit(200) for testing a semiconductor design intellectual property(120) constituting a semiconductor chip internal circuit together with an internal circuit(110), an input data generation part(210) is arranged between the internal circuit and the semiconductor design intellectual property and inputs input signals from the internal circuit and scan data input for a test to the semiconductor design intellectual property selectively according to a scan signal from the external. And an output conversion part(220) converts a test output circuit being output from the semiconductor design intellectual property into serial data and then outputs it to the outside of a semiconductor chip(100).

Abstract translation: 目的：提供半导体设计知识产权测试电路，通过直接输入/输出半导体设计知识产权输入/输出端口的数据模式来测试半导体设计知识产权。 构成：根据用于与内部电路（110）一起构成半导体芯片内部电路的半导体设计知识产权（120）的半导体设计知识产权测试电路（200），输入数据生成部（210） 内部电路和半导体设计知识产权，并根据来自外部的扫描信号，从内部电路输入输入信号和扫描数据输入进行半导体设计知识产权测试。 并且输出转换部分（220）将从半导体设计知识产权输出的测试输出电路转换为串行数据，然后将其输出到半导体芯片（100）的外部。

公开(公告)号：KR1020030047523A

公开(公告)日：2003-06-18

申请号：KR1020010078171

申请日：2001-12-11

Applicant: 한국전자통신연구원

Inventor： 박기혁 ,  엄낙웅 ,  김보우

IPC: G06F7/44

Abstract: PURPOSE: A low-power complex number multiplier is provided to reduce an electric power consumption by operating the optimum multiplier only in the case that a real number and an imaginary number of two input complex numbers are identical. CONSTITUTION: In a complex number multiplier for calculating the product of two complex numbers('x', 'y'), the first multiplier(201) multiplies a real number of 'x' by a real number of 'y'. The second multiplier(202) multiplies an imaginary number of 'x' by an imaginary number of 'y'. The third multiplier(203) multiplies a real number of 'x' by an imaginary number of 'y'. The fourth multiplier(204) multiplies an imaginary number of 'x' by a real number of 'y'. A subtracter(205) calculates a difference of output values of the first multiplier(201) and the second multiplier(202), and calculates a real number of the product of two complex numbers('x', 'y'). An adder(206) calculates the sum of the output values of the third multiplier(203) and the fourth multiplier(204), and calculates an imaginary number of the product of two complex numbers('x', 'y'). A selection unit(300) is included between the third multiplier(203)/the fourth multiplier(204) and the adder(206) for inputting the output values of the first multiplier(201) and the second multiplier(202) to the adder(206) in the case that at least one real number and at least one imaginary number are identical.

Abstract translation: 目的：提供低功率复数乘法器，仅在两个输入复数的实数和虚数相同的情况下通过操作最佳乘法器来降低功耗。 构成：在用于计算两个复数（'x'，'y'）的乘积的复数乘法器中，第一乘法器（201）将实数“x”与实数“y”相乘。 第二乘法器（202）将虚数“x”乘以虚数“y”。 第三乘法器（203）将实数“x”乘以虚数“y”。 第四乘法器（204）将虚数“x”乘以“y”的实数。 减法器（205）计算第一乘法器（201）和第二乘法器（202）的输出值的差，并计算两个复数（'x'，'y'）的乘积的实数。 加法器（206）计算第三乘法器（203）和第四乘法器（204）的输出值的和，并计算两个复数（'x'，'y'）的乘积的虚数。 选择单元（300）包括在第三乘法器（203）/第四乘法器（204）和加法器（206）之间，用于将第一乘法器（201）和第二乘法器（202）的输出值输入到加法器 （206）在至少一个实数和至少一个虚数相同的情况下。

公开(公告)号：KR1020030023286A

公开(公告)日：2003-03-19

申请号：KR1020010056434

申请日：2001-09-13

Applicant: 한국전자통신연구원

Inventor： 권성구 ,  유성욱 ,  박종문 ,  박건식 ,  김보우

IPC: H01L21/28

Abstract: PURPOSE: A semiconductor device having a metal wiring layer completely buried in a hole and fabrication method by using a selective nitridation process are provided to prevent generation of a void and a short circuit when the metal line layer is buried into a contact hole or a via hole. CONSTITUTION: A hole(104) and an interlayer dielectric(103) are formed on a semiconductor substrate(101). The first material layer pattern(105a) is formed on an inner wall and a bottom of the hole(104) and the interlayer dielectric(103). The second material layer pattern(109a) is formed on the first material layer pattern(105a). A metal line layer is formed by burying sequentially the first metal layer pattern(111a), the second metal layer pattern(113a), the third metal layer pattern(115a), and the fourth metal layer pattern(117a) into the hole(104).

Abstract translation: 目的：提供一种将金属布线层完全埋入孔中的半导体器件，并且通过使用选择性氮化处理的制造方法来防止当金属线层埋入接触孔或通孔中时产生空隙和短路 孔。 构成：在半导体基板（101）上形成有孔（104）和层间电介质（103）。 第一材料层图案（105a）形成在孔（104）和层间电介质（103）的内壁和底部上。 第二材料层图案（109a）形成在第一材料层图案（105a）上。 通过将第一金属层图案（111a），第二金属层图案（113a），第三金属层图案（115a）和第四金属层图案（117a）依次埋入孔（104）中而形成金属线层 ）。

公开(公告)号：KR100289066B1

公开(公告)日：2001-11-26

申请号：KR1019970069566

申请日：1997-12-17

Applicant: 한국전자통신연구원

Inventor： 조경익 ,  송윤호 ,  이진호 ,  강승열 ,  김보우

IPC: H01J17/48

Abstract: PURPOSE: A method for manufacturing a conical FED using a conductive thin film deposition process is provided to be stably operated in a low voltage and enable a low temperature process. CONSTITUTION: First, a cathode electrode(22) is formed on an insulating substrate(21). Then, an insulating layer(23) is formed on the cathode electrode, and then a circular mask pattern is formed on a predetermined region of the insulating layer. Next, a conical insulating layer is formed on the cathode electrode by etching the insulating layer exposed using the mask pattern as an etching mask. Then, the mask pattern is removed and the conical insulating layer is etched to form a pointed tip. Finally, a thin film(25) having high heat resistance and low work function is deposited on the conical insulating layer and the cathode electrode.

公开(公告)号：KR100287068B1

公开(公告)日：2001-04-16

申请号：KR1019970073704

申请日：1997-12-24

Applicant: 한국전자통신연구원

Inventor： 이종호 ,  유종선 ,  김보우

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

Abstract: PURPOSE: A structure of a high integrated and a low voltage EEPROM and method for manufacturing thereof are provided to reduce a parasitic junction capacitance component between a source/drain and a substrate and to reduce a writing voltage by performing selectively an ion implanting process on a channel only for controlling a threshold voltage. CONSTITUTION: A channel doping region(2) is formed on a depression portion of a silicon substrate(1). A gate oxide layer(5) is formed onto the channel doping region. A source/drain region(4) is formed symmetrically around the channel doping region of the substrate. A lightly doped drain region(3) is formed on an end portion of the source/drain region near at the channel doping region and is formed in a shape of birds beak. A floating gate(6) is formed on the gate oxide layer. An oxide layer(7) is formed on a surface of a recess formed at an inner of the floating gate. A control gate(8) is formed by filling the inner of the oxide layer. A spacer(9) composed of an insulating material is formed on a side of the floating gate and on a top of the lightly doped drain. An insulating oxide layer is formed onto the adjusting gate and the oxide layer, and the floating gate and the spacer.

公开(公告)号：KR100276431B1

公开(公告)日：2000-12-15

申请号：KR1019970071626

申请日：1997-12-22

Applicant: 한국전자통신연구원

Inventor： 백종태 ,  김윤태 ,  전치훈 ,  김보우

IPC: H01L21/203 ,  B82Y10/00

Abstract: PURPOSE: A method for forming a regular silicon quantum dot and a method for manufacturing a super fine semiconductor device using the same are provided to form a finely uniform quantum dot by using an Si PPT(Precipitation) method. CONSTITUTION: A silicon oxide layer(12) is formed on an upper portion of a silicon substrate(10). A metal-silicon alloy layer is deposited on the silicon oxide layer(12). A silicon ion implantation process is performed on the metal-silicon alloy layer by using a mask(32). A fine Si grain is formed by rearranging Si atoms of the metal-silicon alloy layer. The fine Si grain remains by etching only a metal of the metal-silicon alloy layer.

Abstract translation: 目的：提供用于形成常规硅量子点的方法和使用其的超精细半导体器件的制造方法，以通过使用Si PPT（沉淀）法形成精细均匀的量子点。 构成：在硅衬底（10）的上部形成氧化硅层（12）。 在氧化硅层（12）上沉积金属 - 硅合金层。 通过使用掩模（32）在金属 - 硅合金层上进行硅离子注入工艺。 通过重排金属 - 硅合金层的Si原子形成细的Si晶粒。 通过仅蚀刻金属 - 硅合金层的金属来保留细的Si晶粒。

公开(公告)号：KR100269244B1

公开(公告)日：2000-12-01

申请号：KR1019980019516

申请日：1998-05-28

Applicant: 한국전자통신연구원

Inventor： 김도훈 ,  이각현 ,  최상수 ,  정해빈 ,  김보우

IPC: H01L21/027

CPC classification number: G02B27/0075 ,  G02B5/3083 ,  G03F7/70216

Abstract: PURPOSE: A method for extending depth of focus of an optical system for lithographic equipment using transmission-type optical parts made of a double refraction material is provided to extend a range of an image in a direction of an optical axis, by making the image located in different positions have a predetermined interval in an optical axial direction depending on a polarization component of illumination light. CONSTITUTION: An optical system uses transmission-type double refraction optical parts(210) made of a double refraction material or a double refraction optical unit composed of the optical parts. An image by the double refraction optical unit(200) is focused in different positions and in a direction of an optical axis of the optical system to extend depth of focus, depending on a polarization component of illumination light(20).

Abstract translation: 目的：提供使用由双折射材料制成的透射型光学部件的用于光刻设备的光学系统的焦点深度的方法，以通过使图像位于图像的方向上延伸图像的范围 在不同的位置上，根据照明光的偏振分量，在光轴方向上具有规定的间隔。 构成：光学系统使用由双折射材料制成的透射型双折射光学部件（210）或由光学部件组成的双折射光学单元。 通过双折射光学单元（200）的图像被聚焦在光学系统的光轴的不同位置和方向上，以根据照明光（20）的偏振分量来延长焦深。

公开(公告)号：KR1020000002980A

公开(公告)日：2000-01-15

申请号：KR1019980024011

申请日：1998-06-25

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  이영민 ,  이상복 ,  백종태 ,  김보우

IPC: H01L23/48

CPC classification number: H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19107 ,  H01L2924/00014

Abstract: PURPOSE: A Quad Flat Package(QFP) is provided to minimize the number of electric source and grounding terminals for increasing the number of usable signal terminals. CONSTITUTION: A QFP comprises: an electric source wiring layer(44) and a grounding wiring layer(43); a conductive adhering layer(45) electrically connected to the electric source wiring layer and the grounding wiring layer; a thermal via unit(46) of the QFP electrically connected to the conductive adhering layer; a conductive metal layer(47) electrically connected to the thermal via unit of the QFP; and an electric source pattern and grounding pattern(49) of a printing circuit substrate electrically connected to the conductive metal layer through a connector unit.

Abstract translation: 目的：提供四平面封装（QFP），以最大限度地减少电源和接地端子数量，增加可用信号端子的数量。 构成：QFP包括：电源布线层（44）和接地布线层（43）; 电连接到电源布线层和接地布线层的导电粘合层（45）; 所述QFP的热通孔单元（46）电连接到所述导电粘附层; 电连接到所述QFP的热通孔单元的导电金属层（47）; 以及通过连接器单元电连接到导电金属层的印刷电路基板的电源图案和接地图案（49）。