公开(公告)号：WO2014174710A1

公开(公告)日：2014-10-30

申请号：PCT/JP2013/080268

申请日：2013-11-08

Applicant: 株式会社村田製作所

Inventor： 大坪　喜人 ,  目黒　徹 ,  菅　達典

IPC: H05K3/46 ,  H01L21/66

CPC classification number: H05K1/09 ,  H01L21/4867 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0058 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/4629 ,  H05K3/4644 ,  H05K3/4667 ,  H05K2201/0376 ,  H05K2201/0382 ,  H05K2201/09545 ,  H05K2201/09627 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/1006 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/068 ,  H05K2203/1126 ,  H01L2924/00

Abstract: 　配線構造の高密度化を図り得る多層配線基板を得る。　第１の絶縁層（３）と、第１の絶縁層（３）の下面に積層されている第２の絶縁層（４）とを有する積層体（２）内に、印刷配線電極（７，１１）が設けられており、印刷配線電極（７，１１）が導電ペーストの印刷及び焼成により形成されており、該印刷配線電極（７，１１）が、第２の絶縁層（４）上に位置している第１の配線電極部分（７ａ，１１ａ）と、第１の配線電極部分（７ａ，１１ａ）に連なっている第２の配線電極部分（７ｂ，１１ｂ）とを有し、第２の配線電極部分（７ｂ，１１ｂ）が、貫通孔（３ａ，３ｂ）内に至っており、さらに第１の絶縁層（３）の上面に露出している、多層配線基板（１）。

Abstract translation: 本发明实现了能够实现布线结构的高密度化的多层布线基板。 本发明提供一种多层布线基板（1），其中：印刷布线电极（7,11）设置在层叠体（2）内，该叠层体具有第一绝缘层（3）和第二绝缘层（4） 在所述第一绝缘层（3）的下表面上; 印刷布线电极（7,11）通过印刷和烧结导电浆料形成; 并且印刷布线电极（7,11）具有分别位于第二绝缘层（4）上的第一布线电极部分（7a，11a）和与第二绝缘层（4）连续的第二布线电极部分（7b，11b） 各个第一布线电极部分（7a，11a），所述第二布线电极部分（7b，11b）延伸到相应的通孔（3a，3b）内，并暴露在第一绝缘层（3）的顶表面上。

公开(公告)号：WO2013146931A1

公开(公告)日：2013-10-03

申请号：PCT/JP2013/059111

申请日：2013-03-27

Applicant: 日立化成株式会社

Inventor： 山口　洋志 ,  栗原　清一 ,  桜井　博 ,  貫名　俊介

IPC: H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0154 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2201/10287 ,  H05K2203/061 ,  H05K2203/1572

Abstract: 　多層配線板は、少なくとも２層以上の金属箔配線を有し、表面実装型部品を実装する実装面側に配置される第１の金属箔配線層と、実装面の反対側に配置され、絶縁被覆ワイヤが配線されるワイヤ配線層と、第１の金属箔配線層の表面に位置する金属箔配線を、第１の金属箔配線層の内層の金属箔配線及びワイヤ配線層の絶縁被覆ワイヤの少なくとも一方に電気的に接続する導通部を有する第１の層間導通穴とを備え、第１の層間導通穴の穴径が、多層配線板の板厚方向で異なる。

Abstract translation: 该多层布线基板设置有：第一金属箔布线层，其具有至少两层金属箔布线，并且设置在安装表面安装部件的安装表面侧; 布线层，其布置在安装表面的相反侧上，并且具有布线在其中的绝缘电线; 以及第一中间通孔，具有用于将位于第一金属箔布线层的表面上的金属箔布线电连接到第一金属箔布线层的内层的金属箔布线的导电部分和/ 或布线层的绝缘电线。 第一夹层通孔的直径在多层布线板的板厚度方向上变化。

公开(公告)号：WO2013044002A1

公开(公告)日：2013-03-28

申请号：PCT/US2012/056529

申请日：2012-09-21

Applicant: HARRIS CORPORATION

Inventor： WEATHERSPOON, Michael Raymond ,  RENDEK, Louis Joseph, Jr. ,  SHACKLETTE, Lawrence Wayne ,  RODRIGUEZ, Casey P.

IPC: H05K3/46

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/116 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0141 ,  H05K2201/09545 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method is for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions together.

Abstract translation: 一种用于从电路板层制造多层电路板的方法，每个电路板包括介电层和其上包括第一金属的导电迹线。 该方法包括在第一电路板层中形成通孔，将通孔与第一金属电镀，并将第二金属涂覆到第一电路板层的第一金属上，镀通孔和第一金属 金属。 该方法还包括将第一和第二电路板层对准在一起，使得第一电路板层的电镀通孔与第二电路板层上的特征相邻，并且加热并压紧对准的第一和第二电路板层 以将电介质层层叠在一起，并将相邻的金属部分结合在一起的第一和第二金属的金属间化合物。

公开(公告)号：WO2011072990A3

公开(公告)日：2011-09-15

申请号：PCT/EP2010067964

申请日：2010-11-23

Applicant: IBM ,  IBM UK ,  SU JAMES ,  QUACKENBUSH RICHARD ALAN ,  WILSON JOHN THOMAS

Inventor： SU JAMES ,  QUACKENBUSH RICHARD ALAN ,  WILSON JOHN THOMAS

IPC: H05K1/18

CPC classification number: H05K1/183 ,  H05K3/28 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09545 ,  H05K2201/09781 ,  H05K2201/10189 ,  H05K2203/0228 ,  H05K2203/0242 ,  Y10T29/49156

Abstract: The present invention provides a printed circuit board assembly that includes a first printed circuit board portion having a first thickness and including at least one plated through hole selectively electrically interconnecting electrically conductive layers of the printed circuit board assembly. A second printed circuit board portion is also provided that has a second thickness which is less than the first thickness and further includes another a second plated through hole array exposed on a surface of the second printed circuit board portion.

Abstract translation: 本发明提供了一种印刷电路板组件，其包括具有第一厚度并包括选择性电互连印刷电路板组件的导电层的至少一个电镀通孔的第一印刷电路板部分。 还提供了第二印刷电路板部分，其具有小于第一厚度的第二厚度并且还包括暴露在第二印刷电路板部分的表面上的另一个第二电镀通孔阵列。

公开(公告)号：US20240260168A1

公开(公告)日：2024-08-01

申请号：US18565359

申请日：2022-06-08

Applicant: VITESCO TECHNOLOGIES GMBH

Inventor： Detlev Bagung ,  Christina QUEST-MATT ,  Holger BALDREICH

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/0206 ,  H05K3/0094 ,  H05K3/341 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2201/09609

Abstract: A circuit board (1) for a power semiconductor module (13), having at least one top side (2) and one bottom side (3), wherein at least one mounting area (4) for a power semiconductor component (12) is provided on the top side (2), wherein on the mounting area (4), at least one solder layer (8) is provided for connecting at least one power semiconductor component (12) to the mounting area (4), which layer is divided into regions (9) that are separated from one another by means of intermediate spaces (11), and wherein multiple thermal vias (5) are provided in the circuit board (1) and extend from the top side (2) to the bottom side (3) of the circuit board (2) in the region of the mounting area (4), wherein each upper opening (6) of the thermal vias (5) is directly surrounded by a respective region (9) of the solder layer (8) and each lower opening (7) of the vias (5) is covered by a layer (10) of electrically insulating material.

公开(公告)号：US11864316B2

公开(公告)日：2024-01-02

申请号：US17630630

申请日：2021-07-16

Applicant: Fujikura Ltd.

Inventor： Naoki Oyaizu ,  Yusuke Fujita ,  Toshiaki Inoue ,  Shinya Kashima

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K2201/0305 ,  H05K2201/09481 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.

公开(公告)号：US20230319978A1

公开(公告)日：2023-10-05

申请号：US17713347

申请日：2022-04-05

Applicant: Dell Products L.P.

Inventor： William Andrew Smith ,  Mallikarjun Vasa ,  Bhyrav M. Mutnury

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0218 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09518 ,  H05K2201/09545

Abstract: An information handling system includes a printed circuit board, a surface mount connector including first and second surface mount connector portions, first and second different pairs, and a ground plane. The first and second surface mount connector portions are mounted on the printed circuit board. The first differential pair is located on the first surface mount connector portion, and the second differential pair is located on the second surface mount connector portion. The ground plane is located in between the first and second surface mount connector portions within the printed circuit board. The first ground via is in physical communication with the ground plane and a first ground pad on a surface of the printed circuit board. The second ground via is in physical communication with the ground plane and a second ground pad on the surface of the printed circuit board.

公开(公告)号：US11683886B2

公开(公告)日：2023-06-20

申请号：US17568120

申请日：2022-01-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Toshiki Shirotori

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0959 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

公开(公告)号：US20230180397A1

公开(公告)日：2023-06-08

申请号：US17542867

申请日：2021-12-06

Applicant: R&D Circuits

Inventor： Donald Eric Thompson

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/36 ,  H05K1/18 ,  H05K1/02 ,  C25D7/00 ,  C25D3/38 ,  C25D5/02

CPC classification number: H05K3/426 ,  H05K3/0047 ,  H05K3/368 ,  H05K1/182 ,  H05K1/0222 ,  C25D7/00 ,  C25D3/38 ,  C25D5/02 ,  H05K2201/10325 ,  H05K2201/09072 ,  H05K2201/09545 ,  H05K2203/0723 ,  H05K2201/10409 ,  H05K2201/10303

Abstract: The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.

公开(公告)号：US20180110149A1

公开(公告)日：2018-04-19

申请号：US15559975

申请日：2016-03-23

Applicant: SAFRAN ELECTRONICS & DEFENSE

Inventor： Francois GUILLOT ,  Pascal SPOOR ,  Patrice CHETANNEAU

IPC: H05K7/14 ,  G06F1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K3/42 ,  H01R12/70 ,  H01R12/71

CPC classification number: H05K7/1439 ,  G06F1/184 ,  H01R12/7064 ,  H01R12/716 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/4644 ,  H05K7/1412 ,  H05K7/1445 ,  H05K7/1452 ,  H05K7/1459 ,  H05K2201/0104 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/10189 ,  H05K2201/10295

Abstract: The present invention concerns a backplane electronic board (20) having on inner face (142) suitable for bein g connected to electronic board connectors (12) and an outer face (143) suitable for being connected lo an outer connector (15), the backplane board (20) being characterised in that it has blind holes opening on ihe inner face (142) of some, and holes opening on the outer face (143) of same, the holes being suitable for receiving press-fit connection elements and forming therewith an electrical connection point.