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公开(公告)号：KR1020140146461A
公开(公告)日：2014-12-26
申请号：KR1020130069223
申请日：2013-06-17
Applicant: 삼성전기주식회사
IPC: H05K3/46
Abstract: Disclosed are a printed circuit board and a manufacturing method thereof. According to one aspect of the present invention, provided is the printed circuit board which includes a first insulation layer which includes glass-cloth, a second insulation which is formed on one side of the first insulation layer and does not includes the glass-cloth, a conductive post which passes through the first insulation layer and the second insulation layer, and a first circuit pattern which is formed on the second insulation layer to be electrically connected to the conductive post.
Abstract translation: 公开了一种印刷电路板及其制造方法。 根据本发明的一个方面，提供了一种印刷电路板，其包括：第一绝缘层，其包括玻璃布;第二绝缘体，其形成在所述第一绝缘层的一侧上，并且不包括所述玻璃布; 通过第一绝缘层和第二绝缘层的导电柱，以及形成在第二绝缘层上以电连接到导电柱的第一电路图案。
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公开(公告)号：KR101097628B1
公开(公告)日：2011-12-22
申请号：KR1020100058611
申请日：2010-06-21
Applicant: 삼성전기주식회사
CPC classification number: H05K3/421 , H05K3/0097 , H05K3/426 , H05K3/427 , H05K2201/0959 , H05K2203/1536 , Y10T29/49165
Abstract: PURPOSE: A printed circuit board and a manufacturing method thereof are provided to reduce the size of the printed circuit board or make a solder ball pitch fine. CONSTITUTION: An insulating member(110) includes a via hole(111). A circuit pattern(120) is arranged on the insulating member. A solder resist(140) is arranged on the insulating member. A via plating pad(130) is arranged in the via hole. The via plating pad covers a lower opening of the via hole along with the inner wall of the via hole. An external connection unit(150) includes a central part matched with the central part of the via hole. The external connection unit is arranged on the via plating pad.
Abstract translation: 目的：提供印刷电路板及其制造方法以减小印刷电路板的尺寸或使焊球间距变细。 构成：绝缘构件（110）包括通孔（111）。 电路图案（120）布置在绝缘构件上。 在绝缘部件上设置阻焊剂（140）。 通孔电镀垫（130）布置在通孔中。 通孔电镀垫与通孔的内壁一起覆盖通孔的下开口。 外部连接单元（150）包括与通孔的中心部分相匹配的中心部分。 外部连接单元布置在通孔电镀垫上。
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公开(公告)号：KR1020110128532A
公开(公告)日：2011-11-30
申请号：KR1020100048034
申请日：2010-05-24
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/13
Abstract: PURPOSE: A semiconductor package substrate and a manufacturing method thereof are provided to reduce conspicuously manufacture costs by manufacturing a pair of cross section circuit boards at the same time using a carrier. CONSTITUTION: A circuit pattern is formed in one side of an insulating layer(104) and includes a connection pad. A metal bump(103) is formed in the insulating layer for inter-layer electrical connection. An outer connection terminal is formed on the metal bump of the other side of the insulating layer and is electrically connected with a circuit pattern of one side of the insulating layer through the metal bump. A protective layer(108) is formed on both sides of the insulating layer. The protective layer has an opening which exposes the surface of the metal bump in which the connection pad and the outer connection terminal are formed.
Abstract translation: 目的：提供半导体封装基板及其制造方法，以通过使用载体同时制造一对横截面电路板来减少显着的制造成本。 构成：电路图案形成在绝缘层（104）的一侧，并且包括连接垫。 在用于层间电连接的绝缘层中形成金属凸块（103）。 外绝缘端子形成在绝缘层另一侧的金属凸块上，并通过金属凸块与绝缘层一侧的电路图形电连接。 在绝缘层的两侧形成保护层（108）。 保护层具有露出形成有连接垫和外部连接端子的金属凸块的表面的开口。
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公开(公告)号：KR101013992B1
公开(公告)日：2011-02-14
申请号：KR1020080120966
申请日：2008-12-02
Applicant: 삼성전기주식회사
CPC classification number: B32B37/02 , B32B2457/08 , C25D5/022 , H05K3/205 , H05K3/428 , H05K3/4658 , H05K2201/0376 , H05K2203/0384
Abstract: 인쇄회로기판 제조방법이 개시된다. 층간 접속을 위한 비아를 포함하는 인쇄회로기판을 제조하는 방법으로서, 캐리어의 일면에 회로패턴을 형성하는 단계; 캐리어의 일면을 절연체의 일면에 압착하는 단계; 캐리어를 제거하는 단계; 회로패턴의 일단을 가공하여 절연체를 관통하는 홀을 형성하는 단계; 홀의 내부에, 비아에 상응하도록 도전성 물질을 형성하는 단계를 포함하는 인쇄회로기판 제조방법은, 회로패턴의 밀집도를 높여 제품의 소형화 및 고밀도화를 구현할 수 있다.
인쇄회로기판, 랜드리스, 매립Abstract translation: 公开了一种印刷电路板的制造方法。 一种制造包括用于层间连接的通孔的印刷电路板的方法，包括：在载体的一侧上形成电路图案; 将载体的一个表面压在绝缘体的一个表面上; 移除载体; 通过加工电路图案的一端形成穿过绝缘体的孔; 包括在与通孔对应的孔中形成导电材料的步骤的印刷电路板的制造方法可以增加电路图案的密度并且实现产品的小型化和高密度。
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公开(公告)号：KR1020100010253A
公开(公告)日：2010-02-01
申请号：KR1020080071153
申请日：2008-07-22
Applicant: 삼성전기주식회사
CPC classification number: B32B38/04 , B32B38/10 , B32B2038/0092 , B32B2038/047 , B32B2309/105 , B32B2310/0843 , B32B2457/08 , H05K3/0035 , H05K3/108 , H05K3/421 , H05K3/428 , H05K3/4652 , H05K2201/0376 , H05K2203/0384 , H05K2203/0554 , Y10T156/1056 , Y10T156/1057 , Y10T156/1064 , Y10T156/1082
Abstract: PURPOSE: A method for manufacturing a printed circuit board is provided to easily secure a shape of a via hole by reducing an amount of energy for forming the via hole. CONSTITUTION: A barrier layer is formed on one side of a carrier(S112). A circuit pattern is formed on the barrier layer(S116). A groove corresponding to the via is formed on one side of the carrier(S120). One side of the carrier is compressed to one side of an insulator(S130). The carrier is removed(S140). A via hole corresponding to the groove is formed on the insulator(S150). A conductive material is formed inside the via hole(S160).
Abstract translation: 目的：提供一种制造印刷电路板的方法，通过减少用于形成通孔的能量来容易地确保通孔的形状。 构成：在载体的一侧形成阻挡层（S112）。 在阻挡层上形成电路图案（S116）。 在载体的一侧形成与通孔相对应的槽（S120）。 载体的一侧被压缩到绝缘体的一侧（S130）。 移除载体（S140）。 在绝缘体上形成与沟槽对应的通路孔（S150）。 导电材料形成在通孔内（S160）。
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Patent Agency Ranking
公开(公告)号：KR100905566B1
公开(公告)日：2009-07-02
申请号：KR1020070042002
申请日：2007-04-30
Applicant: 삼성전기주식회사
IPC: H05K3/00
CPC classification number: H05K3/428 , H05K3/205 , H05K3/383 , H05K3/384 , H05K3/4602 , H05K3/4658 , H05K2201/0394 , H05K2201/09563 , H05K2203/1536 , Y10T29/49155
Abstract: 본 발명은 회로 전사용 캐리어 부재, 이를 이용한 코어리스 인쇄회로기판, 및 이들의 제조방법에 관한 것으로서, 캐리어층의 일면에 베리어층과, 외측 상단에만 요철이 형성되어 있는 회로 패턴을 갖도록 구성된 회로 전사용 캐리어 부재를 이용하여 회로 패턴을 수지 절연층에 전사하여 매립함으로써 고밀도, 고신뢰도의 코어리스 인쇄회로기판을 제작할 수 있다.
회로 전사용 캐리어, 코어리스, 인쇄회로기판, 베리어층, 절연층-
公开(公告)号：KR1020090002718A
公开(公告)日：2009-01-09
申请号：KR1020070066894
申请日：2007-07-04
Applicant: 삼성전기주식회사
IPC: H05K3/00
CPC classification number: H05K3/205 , H05K3/108 , H05K3/4602 , H05K2203/1536 , Y10T428/249984 , Y10T428/31504 , Y10T428/31511 , Y10T428/3154 , Y10T428/31678 , Y10T428/31721 , Y10T428/31993
Abstract: The carrier and manufacturing method of PCB are provided to shorten the manufacturing process by forming the circuit pattern on a pair of releasing layer through one process. The carrier(10) comprises the base material layer(12), and a pair of the bonding layer(14) and pair of the releasing layer(16). A pair of bonding layer is laminated on both sides of the base material layer. The adhesive force of a pair of bonding layer is degraded by the predetermined factor. A pair of releasing layer is adhered at each bonding layer. The releasing layer comprises one of the conductive metal or the insulating material.
Abstract translation: 提供PCB的载体和制造方法，以通过一个工艺在一对释放层上形成电路图案来缩短制造过程。 载体（10）包括基材层（12）和一对粘合层（14）和一对释放层（16）。 在基材层的两侧层叠一对接合层。 一对结合层的粘合力降低预定因子。 在每个接合层处粘附一对释放层。 释放层包括导电金属或绝缘材料之一。
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公开(公告)号：KR1020080096985A
公开(公告)日：2008-11-04
申请号：KR1020070042002
申请日：2007-04-30
Applicant: 삼성전기주식회사
IPC: H05K3/00
CPC classification number: H05K3/428 , H05K3/205 , H05K3/383 , H05K3/384 , H05K3/4602 , H05K3/4658 , H05K2201/0394 , H05K2201/09563 , H05K2203/1536 , Y10T29/49155
Abstract: A carrier member for transferring circuits, a coreless printed circuit board using the same, and methods for manufacturing the same minimize damage to circuits and improve reliability of the printed circuit board by forming a concavo-convex only in the bottom of an inner side of a circuit pattern. A carrier plate composed of a carrier layer(302a, 302b) and a barrier layer(303a, 303b) on both sides of thermal adhesive representing non-adhesive property in a thermal process is attached to both sides carrier structure. The barrier layer is the metal seed layer except copper. A plating resist is coated on the part including lands or the part except for the circuit formation part which does not include the lands, on the barrier layer of the both sides carrier structure. The circuit pattern is formed by electro copper plating the opened circuit formation part through the plating resist. The concavo-convex part is formed by roughing an exposed surface of the circuit pattern. A pair of carrier members for transferring circuits is obtained and separated from the thermal adhesive by removing the plating resist and thermal treating both sides carrier structure.
Abstract translation: 用于传送电路的载体构件，使用其的无芯无线印刷电路板及其制造方法使对电路的损害最小化，并且仅通过在内侧的底部形成凹凸来提高印刷电路板的可靠性 电路图案。 在热处理中代表非粘合性的热粘合剂两侧的载体层（302a，302b）和阻挡层（303a，303b）构成的载体板被安装在两侧载体结构上。 阻挡层是铜以外的金属种子层。 在两面载体结构的阻挡层上，在包括焊盘或除了不包括焊盘的电路形成部分的部分之外的部分上涂覆电镀抗蚀剂。 电路图案是通过电镀抗蚀剂对开路形成部分进行电镀铜而形成的。 凹凸部通过粗糙化电路图案的露出表面而形成。 通过去除电镀抗蚀剂和热处理双面载体结构，获得用于转移电路的一对载体构件并与热粘合剂分离。
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公开(公告)号：KR1020080037307A
公开(公告)日：2008-04-30
申请号：KR1020060104203
申请日：2006-10-25
Applicant: 삼성전기주식회사
IPC: H05K3/20
CPC classification number: H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
Abstract: A circuit board and a method for manufacturing the same are provided to reduce a thickness of the entire circuit board and a material cost by forming the multi-layered circuit board without addition of an insulator. A method for manufacturing a circuit board includes the steps of: forming a conductive relief pattern with a sequentially stacked first plating layer, a first metal layer, and a second plating layer on a seed layer of a carrier with the stacked seed layers to correspond to a first circuit pattern(S100); stacking an insulator and one surface of the carrier with the conductive relief pattern to face each other and compressing the stacked insulator and carrier(S200); transferring the conductive relief pattern to the insulator by removing the carrier(S300); forming a conductive pattern with the sequentially stacked third plating layer and the second metal layer on one surface of the insulator with the transferred conductive relief pattern to correspond to a second circuit pattern(S400); removing the first plating layer and the seed layer(S500); and removing the first metal layer and the second metal layer(S600).
Abstract translation: 提供一种电路板及其制造方法，以通过在不添加绝缘体的情况下形成多层电路板来减小整个电路板的厚度和材料成本。 一种电路板的制造方法，其特征在于，具有：在层叠种子层的载体的种子层上形成具有顺序层叠的第一镀层，第一金属层和第二镀层的导电性浮雕图案，以对应于 第一电路图案（S100）; 用导电凸版图案堆叠绝缘体和载体的一个表面以彼此面对并压缩堆叠的绝缘体和载体（S200）; 通过移除载体将导电浮雕图案转印到绝缘体上（S300）; 在所述绝缘体的一个表面上依次堆叠的第三镀层和所述第二金属层与所述转移的导电浮雕图案形成导电图案以对应于第二电路图案（S400）; 去除第一镀层和种子层（S500）; 并移除第一金属层和第二金属层（S600）。
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公开(公告)号：KR100792352B1
公开(公告)日：2008-01-08
申请号：KR1020060063633
申请日：2006-07-06
Applicant: 삼성전기주식회사
IPC: H01L23/12
CPC classification number: H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06568 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A bottom substrate of a POP(Package On Package) and a method of manufacturing the same are provided to increase the number of integrated circuits mounted thereon without increasing a size of a solder ball. A bottom substrate of a POP is electrically connected to a top substrate by using a solder ball. The bottom substrate includes a core substrate(10), a solder ball pad(12) formed on a surface of the core substrate corresponding to a position of the solder ball, an insulating layer(20) stacked on the core substrate, a through-hole formed by removing a solder ball pad part from the insulating layer to expose the solder ball pad, and a metal layer(28) for filling up the through-hole. The metal layer is electrically connected to the solder ball. The insulating layer is formed by stacking photoresist on the core substrate and hardening the photoresist.
Abstract translation: 提供POP（封装封装）的底部基板及其制造方法以增加其上安装的集成电路的数量，而不增加焊球的尺寸。 POP的底部基板通过使用焊球与顶部基板电连接。 底部基板包括芯基板（10），形成在对应于焊球位置的芯基板的表面上的焊球垫（12），堆叠在芯基板上的绝缘层（20） 通过从绝缘层去除焊球焊盘部分以暴露焊球焊盘而形成的孔，以及用于填充通孔的金属层（28）。 金属层电连接到焊球。 绝缘层通过在芯基板上堆叠光致抗蚀剂并使光致抗蚀剂硬化而形成。
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