公开(公告)号：DE60031860D1

公开(公告)日：2006-12-28

申请号：DE60031860

申请日：2000-11-23

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  PIERIN ANDREA ,  GREGORI STEFANO ,  TORELLI GUIDO

IPC: H03M1/14 ,  G11C11/56

公开(公告)号：DE60305104D1

公开(公告)日：2006-06-14

申请号：DE60305104

申请日：2003-07-04

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  MOTTA ILARIA ,  CAPOVILLA MARCO

IPC: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C16/12

Abstract: Voltage booster device (3) such as to selectively assume an active status and a stand-by status, said device comprising: a first terminal (15) such as to assume a respective electric potential and associated to a first capacitor (16), a second terminal (10) associated to a second capacitor (11) and selectively connectable to the first terminal (15), characterised in that it also comprises circuital means (100) for discharging the first capacitor thus reducing in module the electrical potential of the first terminal (15), the circuital means being activated to functioning when said device in the stand-by status and the second terminal (10) is disconnected from said first terminal (15).

公开(公告)号：DE69927364D1

公开(公告)日：2005-10-27

申请号：DE69927364

申请日：1999-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  SACCO ANDREA ,  PICCA MASSIMILIANO

IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10 ,  G11C8/00

Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

公开(公告)号：DE60020210D1

公开(公告)日：2005-06-23

申请号：DE60020210

申请日：2000-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： MANSTRETTA ALESSANDRO ,  MICHELONI RINO ,  PIERIN ANDREA ,  YERO EMILIO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

公开(公告)号：DE69629669T2

公开(公告)日：2004-07-08

申请号：DE69629669

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO

IPC: G11C16/28 ,  G11C16/06

Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (IR1) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (IB) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

公开(公告)号：DE69728148D1

公开(公告)日：2004-04-22

申请号：DE69728148

申请日：1997-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO ,  ZAMMATTIO MATTEO

IPC: G11C8/18 ,  G11C8/00

公开(公告)号：IT1320699B1

公开(公告)日：2003-12-10

申请号：ITTO20000936

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  GREGORI STEFANO ,  KHOURI OSAMA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/30

Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

公开(公告)号：DE69630024D1

公开(公告)日：2003-10-23

申请号：DE69630024

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  COMMODARO STEFANO

IPC: G11C16/28 ,  G11C16/06

Abstract: A nonvolatile memory (35) presenting a data memory array (2) including memory cells 85); a read circuit (40) including a plurality of sense amplifiers (10), each connected to a respective array branch (17) to be connected to the memory cells; and a reference generating circuit (55) including a single reference cell (60) arranged outside the data memory array (2) and generating a reference signal (IR). The reference generating circuit (55) presents a plurality of reference branches (41), each connected to a respective sense amplifier (10); and current mirror circuits (53, 54, 62, 63) interposed between the reference cell (60) and the reference branches (41), and supplying the reference branches with the reference signal (IR).

公开(公告)号：DE69629669D1

公开(公告)日：2003-10-02

申请号：DE69629669

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO

IPC: G11C16/28 ,  G11C16/06

Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (IR1) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (IB) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

公开(公告)号：ITTO20010529A1

公开(公告)日：2002-12-02

申请号：ITTO20010529

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

IPC: G06F11/10 ,  G06F12/00

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.