公开(公告)号：US09872393B2

公开(公告)日：2018-01-16

申请号：US14886581

申请日：2015-10-19

Applicant: Avary Holding (Shenzhen) Co., Limited ,  HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  GARUDA TECHNOLOGY CO., LTD.

Inventor： Tzu-Chien Yeh

IPC: H01K3/10 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K1/09 ,  H05K1/03 ,  H05K3/18 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/184 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/111 ,  H05K1/115 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/0203 ,  H05K2201/0391 ,  H05K2201/09545 ,  H05K2203/0278 ,  H05K2203/122 ,  H05K2203/1536 ,  Y10T29/49165

Abstract: A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between and connected to one passive component and the first conductive wire layer. The resin packing layer is filled among the core layer, each passive component, each contact pad, the first and the second conductive wire layers. The resin packing layer can connect the first and the second conductive wire layers to the core layer, and connect the core layer, each passive component, and each contact pads to each other.

公开(公告)号：US09867290B2

公开(公告)日：2018-01-09

申请号：US14834205

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

公开(公告)号：US09775231B2

公开(公告)日：2017-09-26

申请号：US14947091

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Marc B. Cartier, Jr.

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11 ,  H01R43/20

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

公开(公告)号：US09761972B2

公开(公告)日：2017-09-12

申请号：US15200695

申请日：2016-07-01

Applicant: MERCURY SYSTEMS, INC.

Inventor： Philip Beucler ,  Daniel Coolidge ,  Darryl J. McKenney ,  Kevin Jorczak

IPC: H01R9/05 ,  H01R12/71 ,  H01R12/58 ,  H01R13/652 ,  H05K1/18 ,  H05K3/34 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01R12/716 ,  H01R4/028 ,  H01R9/091 ,  H01R12/526 ,  H01R12/58 ,  H01R12/714 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/421 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10878 ,  H05K2201/10901 ,  Y02P70/611

Abstract: An RF connector includes a conductive pin for carrying an RF signal. The conductive pin has a first longitudinal end that serves to interface with a male RF connector to receive the RF signal. The pin also includes a second longitudinal end for connecting with a printed circuit board (PCB). The second longitudinal end may be tapered, and the pin may have a groove formed above the tapered end. A housing encircles the conductive pin. The housing is shaped and sized to accept the male RF connector. A grounding element may be positioned on the bottom of the housing. The grounding element is to contact the PCB when the connector is connected to the PCB. The grounding element may be ring-shaped and soldered to the housing or epoxied to the housing.

公开(公告)号：US09706656B2

公开(公告)日：2017-07-11

申请号：US14950584

申请日：2015-11-24

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Jing-Yao Chang ,  Tao-Chih Chang ,  Ren-Shin Cheng ,  Min-Lin Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0251 ,  H05K3/42 ,  H05K2201/0187 ,  H05K2201/09545 ,  H05K2203/1105 ,  H05K2203/1178 ,  H05K2203/143 ,  H05K2203/1438

Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

公开(公告)号：US20170150592A1

公开(公告)日：2017-05-25

申请号：US15423584

申请日：2017-02-03

Applicant: MPI corporation

Inventor： WEI-CHENG KU ,  JUN-LIANG LAI ,  CHIH-HAO HO

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/18 ,  H05K3/421 ,  H05K3/426 ,  H05K3/429 ,  H05K2201/041 ,  H05K2201/09545 ,  H05K2203/0369 ,  H05K2203/1461

Abstract: A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with two first pads, two second pads, and two first sub-circuits. The first pads and the second pads are electrically connected to the first sub-circuits. The second substrate has a top surface, a bottom surface, a lateral edge, and two openings. The bottom surface of the second substrate is attached to the top surface of the first substrate. The openings extend from the top surface to the bottom surface of the second substrate. The first pads of the first substrate are in the opening of the second substrate; the second pads of the first substrate are not covered by the second substrate. The second substrate is further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.

公开(公告)号：US20170027057A1

公开(公告)日：2017-01-26

申请号：US15216735

申请日：2016-07-22

Applicant: IBIDEN CO., LTD.

Inventor： Masatoshi KUNIEDA ,  Takafumi OKUMURA

IPC: H05K1/11 ,  H01L23/31 ,  H05K1/09 ,  H01L23/00 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K1/115 ,  H01L23/3114 ,  H01L24/14 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H05K3/185 ,  H05K3/422 ,  H05K3/424 ,  H05K2201/09545 ,  H05K2201/09627 ,  H05K2201/09645 ,  H05K2203/0723

Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.

Abstract translation: 一种制造印刷电路板的方法包括在绝缘层的表面上形成图案化催化剂膜，该图案化催化剂膜包括用于化学镀的催化剂，使得图案化的催化剂膜具有与导体电路相对应的图案，并且在 图案化的催化剂膜，使得导体金属沉积在图案化的催化剂膜上，并且导体电路形成在绝缘层的表面上。

公开(公告)号：US09491881B2

公开(公告)日：2016-11-08

申请号：US14164403

申请日：2014-01-27

Applicant: Joshua D. Heppner ,  Zhichao Zhang ,  Srikant Nekkanty ,  Michael Garcia

Inventor： Joshua D. Heppner ,  Zhichao Zhang ,  Srikant Nekkanty ,  Michael Garcia

IPC: H05K7/10 ,  H01R12/70 ,  H05K1/18 ,  H05K3/42

CPC classification number: H05K7/1069 ,  H01R12/7076 ,  H01R12/7082 ,  H05K1/184 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10189 ,  H05K2201/10265 ,  Y10T29/49222

Abstract: A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via.

Abstract translation: 一种具有两件式结构的微电子插座，其中第一件包括导电插座衬底，第二件包括绝缘插入件。 导电插座基板具有第一表面，第二表面和在它们之间延伸的至少一个开口。 绝缘插入件具有从其延伸的至少一个突起的基部。 绝缘插入件与导电插座基板配合，使得至少一个突起位于相应的导电插座衬底开口内。 绝缘插入件还包括多个通孔，其中多个通孔中的至少一个延伸穿过绝缘基底并穿过绝缘插入物突起，其中触点可以设置在通孔内。

公开(公告)号：US20160278208A1

公开(公告)日：2016-09-22

申请号：US14834205

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/42 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract translation: 用于制造电路板的选择性段通过电镀工艺选择性地将内部导电层互连在相同的通孔内的单独的段。 将电镀抗蚀剂施加到内芯的导电层，然后在无电镀处理之后剥离。 在电镀抗蚀剂上剥离化学镀导致通孔壁上的电镀不连续。 在随后的电镀工艺中，由于电镀不连续性，插头非导电层不能镀覆。 所得到的电路板结构在通孔内具有单独的电互连段。

公开(公告)号：US20160057866A1

公开(公告)日：2016-02-25

申请号：US14463012

申请日：2014-08-19

Applicant: JSR CORPORATION

Inventor： Sugirou SHIMODA ,  Kenzou Ookita ,  Isao Aritome ,  Kazuto Watanabe ,  Kenrou Tanaka

IPC: H05K3/00 ,  H01L23/48 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  C08K5/17 ,  H05K1/09 ,  H05K1/02 ,  C09D11/52 ,  C08K5/098 ,  C08K3/22 ,  C08K5/07 ,  H01B13/00 ,  H01L21/288

CPC classification number: C08K5/17 ,  C08K3/22 ,  C08K5/07 ,  C08K5/098 ,  C08K2003/2248 ,  C09D11/037 ,  C09D11/38 ,  C09D11/52 ,  H01L21/288 ,  H01L21/4846 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49883 ,  H01L27/1085 ,  H01L28/60 ,  H01L2924/0002 ,  H05K3/105 ,  H05K3/4076 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09545 ,  H01L2924/00

Abstract: An object of the invention is to provide a simple method capable of easily forming a metal film on a surface of a perforated substrate that is adjacent to the hole in the substrate. The metal film forming method includes a step of heating a perforated substrate having a hole while a surface of the substrate adjacent to the hole is in contact with a conductive ink containing a metal salt and a reducing agent.

Abstract translation: 本发明的目的是提供一种能够容易地在与基板中的孔相邻的多孔基板的表面上形成金属膜的简单方法。 金属膜形成方法包括加热具有孔的多孔基材的步骤，同时邻近孔的基板的表面与含有金属盐和还原剂的导电油墨接触。