公开(公告)号：JPH08236520A

公开(公告)日：1996-09-13

申请号：JP28700995

申请日：1995-11-06

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU SATOSHI ,  GU CHINKON

IPC: H01L21/768 ,  H01L21/265 ,  H01L21/31 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To harden an SOG film so that any residual substance can not be generated by forming a second insulating film by SOG on a first insulating film on a substrate, operating a low temperature processing and a plasma processing for hardening the second insulating film, and forming a third insulating film. SOLUTION: A first insulating film 5 is formed by forming an oxide film by a PECVD method. The spin coating of SOG substances is operated for flattening the surface so that a second insulating film 7 can be formed. A low temperature thermal processing is executed several times while a temperature is successively increased, and solvent components, volatile organic components, and moisture excluding organic substances used as coupling agent included in the second insulating film 7 are removed. A plasma processing is executed to the second insulating film 7, and residual substances such as Si-OH, H2 O, solvent, and volatile organic substances are removed so that a membranous quality with high elasticity can be formed. A third insulating film 9 is formed so that an insulating layer 11 can be completed. Thus, it is possible to prevent the current/voltage characteristics of the SOG film from being deteriorated.

公开(公告)号：JPH08186165A

公开(公告)日：1996-07-16

申请号：JP31481394

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： REN HEIRETSU ,  KAN TAIGEN ,  RI SHIYUUMIN ,  CHIYOU TOKUKOU ,  RI SEIHAAN ,  KIYOU CHINEI

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/737

Abstract: PURPOSE: To obtain a method for producing an isolated SOI(Silicon on Insulator) in which the reliability is enhanced by planarizing a thin film completely through a simple process regardless of the pattern density or the uniformity of the surface while facilitating control of the thickness of each thin film constituting the substrate. CONSTITUTION: The SOI substrate comprises a second insulation layer 23b formed on the entire surface of a substrate 27 bonded directly thereto, a first insulation layer 23a formed on the second insulation layer 23b and planarized, and an active layer 31 isolated through the first insulation layer 23a.

公开(公告)号：JPH08186128A

公开(公告)日：1996-07-16

申请号：JP31538694

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI SHINKI ,  SAI SOUSHIYU ,  IN KIYOUSHIYOU ,  BOKU CHIYURUJIYUN ,  YU KEISHIYUN ,  BOKU KIYOUMO

IPC: H01L21/027 ,  H01L21/336 ,  H01L21/338 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

Abstract: PURPOSE: To reduce the resistance and parasitic capacitance of a fine gate by irradiating the upper and lower parts of the gate with an electron beam having different intensity of energy. CONSTITUTION: A two-dimensional electron gas layer 2, an AlGaAs layer 3 and a doped Schottky layer, i.e., a cap layer 4, are formed sequentially on a substrate 1 followed by formation of ohmic layers 5a, 5b. A resist 6 is then applied to the cap layer 4 and heat treated. Subsequently, a second resist 7 is applied onto the first resist 6 and an exposure step is executed using an electron beam having uneven energy. In order to form a T type gate, first and third electron beams 8a, 8c have energy of such intensity as exposing only the second resist 7 while a second electron beam 8b has energy of such intensity the first and second resists 6, 7 can be exposed entirely.

公开(公告)号：JPH08167909A

公开(公告)日：1996-06-25

申请号：JP24347295

申请日：1995-09-21

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： YU GORU U ,  JIYON TE SUYU

IPC: H04Q3/00 ,  H04L12/931 ,  H04Q3/52 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To process high speed data received/outputted to/from each input/ output line without increasing a speed of the switch through decentralized processing by which lots of input cells are sent simultaneously to each output line and through ease of module realization. SOLUTION: The switch is provided with a batcher sorting network(BSN) 401 that arranges N cells received simultaneously through an input line of the switch in the order of smaller to larger cells, an expanded Banyan routing network(EBRN) 402 that provides an output of the arranged cells from the BSN 401 to an output line group to which output lines belong, and an output queuing module 403 that temporarily stores cells outputted from the EBRN 402 to a buffer of a common memory and transmits them to an output terminal.

公开(公告)号：JPH08163116A

公开(公告)日：1996-06-21

申请号：JP31645094

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIYO SEIIKU ,  KIN HOSHIMICHI ,  TEI KIHAN ,  SOU GENTETSU ,  RI KUNFUKU

IPC: H04M7/08 ,  H04J3/00 ,  H04J3/06 ,  H04L7/08

Abstract: PURPOSE: To realize the frame synchronization device to demultiplex a time division multiplex signal in parallel from an STM-4C structure of a broad band overall information communication network in compliance with the ITU-T recommendations. CONSTITUTION: A serial parallel conversion circuit 10 and a byte arrangement circuit 30 detect a frame byte from high speed reception data at a transmission rate of 622 Mbps, align bytes based on a detected time and provides an output of frame data as 8-bit parallel data. A synchronizing signal pattern detection circuit 90 and a consecutive pattern confirmation circuit 100 detect frame bytes continuously based on a low speed clock obtained by applying 8 frequency division from an original clock signal at a frequency divider circuit 70 to seek a frame synchronizing signal. As a result, the power consumption is reduced and the amount of the hardware is decreased.

公开(公告)号：JPH08163097A

公开(公告)日：1996-06-21

申请号：JP6813995

申请日：1995-03-27

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RIYU GABU YORU ,  BAKU CHIYAN SUYU

IPC: G02B6/26 ,  H01S5/0687 ,  H01S5/40 ,  H04B10/071 ,  H04J14/00 ,  H04J14/02

Abstract: PURPOSE: To maximize the number of multiplexing light sources by enhancing the extinction ratio of an error signal. CONSTITUTION: A center carrier frequency of each light source 13 is dithered by a low frequency signal from each low frequency oscillator 11. Optical signals from the light sources are coupled by a 2×2 photocoupler 15. One output from the photocoupler 15 is sent externally as a final multiplexed output and the other output is fed to an optical fiber filter 17 in a resonance means via a 2×1 photocoupler 16. The optical signal reflected in the filter 17 is converted into an electric signal by a photo detector 18 via the photocoupler 16 and the electric signal is fed to an optical frequency stabilizing controller 19. A PID circuit 20 in the controller 19 detects an error signal, it is converted into a corresponding current by a PSD circuit 21 and the current is applied as a bias to the light sources 13. Since center carrier frequencies f1-fn of the light sources 13 are aligned corresponding to resonance frequencies f1'-fn' of the resonator by repeating the process above, an output that is optical-frequency-multiplexed at an equal interval is obtained.

公开(公告)号：JPH08162636A

公开(公告)日：1996-06-21

申请号：JP31538894

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SEIGEN ,  KIYOU GENKIYUU ,  KIN JIYOKAN ,  YANAGI SHIYOUZEN

IPC: H01L21/768 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: PURPOSE: To provide a field-effect element and its electrode forming method capable for forming the electric contacts of an element aligning them automatically, without a contact hole forming process, in a wiring process between electrodes of a kind of silicon, metal or different kinds of metals. CONSTITUTION: Parts of an insulating film 48 on field oxide films 40 and on parts where electrode contacts of wiring electrodes, electrodes of a kind of silicon, electrodes of different kinds of metals are formed are removed, and only parts surrounding the region of a gate electrode, i.e., gate oxide films 48a, 48b are left unremoved. And a substance for wiring electrodes is applied, and the substance is patterned after that and wiring electrodes 49 are formed.

公开(公告)号：JPH08160406A

公开(公告)日：1996-06-21

申请号：JP31506894

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： MINAMI MOTOMORI ,  BOKU SHINSHIYOU ,  KIN HISAHIRO ,  BOKU SOUSHIYUN

IPC: G02F1/1333 ,  G02F1/13 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/35 ,  H01L21/336 ,  H01L29/786

Abstract: PURPOSE: To provide a method for manufacturing a large area flat display utilizing side joint, so as to obtain a large area via the use of the side jointing method. CONSTITUTION: A product technology for realizing a large screen by use of the thin film transistor technology is provided under the application of the entirely unique method of side jointing. In this case, a thin film transistor unit panel 2 is manufactured through a process for the side jointing to form a large area at a side jointing process, and a process for jointing a large area thin film transistor panel 4 to a common electrode panel 5.

公开(公告)号：JPH08148990A

公开(公告)日：1996-06-07

申请号：JP31048194

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN CHINGIYOU ,  KIN ZENEI

IPC: G06F7/50 ,  G06F7/44 ,  G06F7/49 ,  G06F7/501 ,  H03K19/20

Abstract: PURPOSE: To provide the operation device of AND logic, which defines the operation rule of AND for operating AND on multi-nary logics while the AND of binary numbers is contained, by containing an operation adder for obtaining a multi-nary logic value fitted to the input of the binary number and the computing element of binary-nary AND for receiving the output of the operation adder and binary input. CONSTITUTION: The AND logic operator 52 receiving the three inputs of multi- nary logic is configured of two AND logic operators 51 receiving two inputs. Such operation device of multi-nary AND logic contains the operation function of existed binary AND and the operation function of binary-multi-nary AND. For calculating the output of the logic circuit by using the binary-multi-nary AND logic operator, the operation circuit is constituted of only one binary- multi-nay AND logic operator and one operation adder. When the multi-nary AND logic operator is used, the configuration of the circuit and the like for operating the multi-nary logic value can be simplified.

公开(公告)号：JPH08148729A

公开(公告)日：1996-06-07

申请号：JP29744094

申请日：1994-11-30

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SEI KENYON ,  JO MASAHIRO

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/14 ,  H01L39/24

Abstract: PURPOSE: To provide the manufacture of a thick superconducting field-effect transistor having a superconducting channel. CONSTITUTION: A template layer 32 and a YBa2 Cu3 O7-x layer 34 are formed successively onto the surface of the crystal substrate 30 of an oxide. A part of the YBa2 Cu3 O7-x layer 34 is removed (an opening section 35), and the layer 32 is exposed. The surfaces are covered with a YBa2 Cu3 O7-x channel layer 36 in thickness of 60-100 mm. An SrTiO3 protective layer 38 and an SrTiO3 insulating layer 40 are formed successively onto the channel layer 36. Parts of the insulation layer 40 and the protective layer 38 are removed by dry etching, and parts of the channel layer 36 are exposed. Source/drain electrodes 44, 46 are formed onto the surface of the cannel layer 36. A gate electrode 42 is formed simultaneously onto the insulating layer 40 in the opening section 35. Accordingly, the productivity and the characteristics of the superconducting FET are improved.