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公开(公告)号：JPH07326195A
公开(公告)日：1995-12-12
申请号：JP5656995
申请日：1995-02-21
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , OLIVO MARCO
Abstract: PURPOSE: To prevent the occurrence of erase and change of contents of non- specified memory cells by providing a normally-open switch and a current generator to control a discharge current. CONSTITUTION: A memory cell 5 to be erased is specified. For performing the erasing, a programming voltage Vpp from a logical switch SW is connected to the cell to set a source line SRC a high voltage a normally-open switch 11 of control transistors M2 and M3 and an erase transistor M4. After completion of the erase stage, the line SRC has an erase voltage value higher than the high potential, which voltage is discharged to the ground. This causes a signal SL to be set at its high level, thus turning a switch I1 ON. This causes the voltage of the line SRC to be controlled by a current IS to continue slow discharging operation. In this way, since the discharging operation of the source line SRC is controlled to be gradually slow, the occurrence of erase/change of contents of the memory cells 5 other than the specified cell can be prevented.
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公开(公告)号：JPH07319565A
公开(公告)日：1995-12-08
申请号：JP13588595
申请日：1995-05-08
Applicant: ST MICROELECTRONICS SRL
Inventor： PEDRAZZINI GIORGIO , SCROCCHI GIUSEPPE , CORDINI PAOLO , ROSSI DOMENICO
Abstract: PURPOSE: To provide a PWM control circuit for operating current mode control in a complete digital mode without necessitating the usage of any error amplifier, or excessively complicating the circuit. CONSTITUTION: This circuit includes first and second comparators COMP 1 and 2 for a sense resistance RSENSE, and a bi-directional stable logic circuit FFD 2 driven by the output of the second comparator COMP 2, which can generate a logical signal supplied to the third input of a bi-directional stable logic circuit FFD 1 for prohibiting the usage of a power switch Ml only in a preliminarily set time.
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公开(公告)号：JPH07282202A
公开(公告)日：1995-10-27
申请号：JP350395
申请日：1995-01-12
Applicant: ST MICROELECTRONICS SRL
Inventor： KOVACS ZSOLT
Abstract: PURPOSE: To provide an alphanumeric letter image recognition device whose recognition quality is more excellent than that of a conventional well-known recognition device in a scientific and industrial environment. CONSTITUTION: A 2nd stage 3 in the alphanumeric letter image recognition device 1 includes 1st and 2nd statistic circuit networks ST1, ST2, 1st and 2nd input terminals of the 1st statistic circuit network ST1 are connected respectively to output terminals of 1st and 2nd memory registers REG1, REG2, 1st and 2nd input terminals of the 2nd statistic circuit network ST2 are connected respectively to output terminals of 2nd and 3rd memory registers REG2, REG3, and the 2nd stage 3 includes a 3rd statistic circuit network STOUT having a plurality of input terminals connecting to a plurality of output terminals of the 1st and 2nd statistic circuit networks ST1, ST2 and a plurality of output terminals being output terminals of the alphanumeric letter image recognition device 1.
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154.发明专利
公开(公告)号：JPH07273627A
公开(公告)日：1995-10-20
申请号：JP9797595
申请日：1995-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： BERTOLINI LUCA
IPC: H01L27/04 , H01L21/822 , H01L29/78 , H02H9/04 , H03K17/00 , H03K17/08 , H03K17/082 , H03K17/615 , H03K17/687
Abstract: PURPOSE: To provide a power stage which can evade the loss of the accuracy of the circuit due to current absorption because a current is possibly absorbed at an output node of a circuit using a couple of Zener diodes connected reversely in parallel. CONSTITUTION: A bipolar transistor Q1 for decoupling the output node Vo of the power stage from a 2nd field effect transistor M2 is installed. When the Zener diodes D1 and D2 absorb a current Id, this current is supplied from the transistor Q1, which absorbs it from a high voltage node Vb.
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公开(公告)号：JPH07273563A
公开(公告)日：1995-10-20
申请号：JP32798494
申请日：1994-12-28
Applicant: ST MICROELECTRONICS SRL
Inventor： TAVAZZANI CLAUDIO , FASSINA ANDREA , STEFANI FABRIZIO
Abstract: PURPOSE: To obtain the amplification state protecting circuit which is reduced in the total number of circuit elements, specially, sense circuits and therefore improved in the reliability of protection and decreased in the integration area of the circuit. CONSTITUTION: This circuit is provided with a circuit switching means G which is piloted by a logic OR gate F by a monostable M and generates a turn-on command signal with predetermined continuation duration in case of an abnormal operating conditions. After a sense circuit B which senses an abnormal state at a start or in the normal operation enables an AND gate H, a turn-off signal is sent through the OR gate. The signal of the AND gate arrives as a confirmation signal through an OR logic gate C from a window comparator A coupled with an amplification stage start member, a monostable flip-flop, and the output terminal of the AND gate H.
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Patent Agency Ranking156.发明专利
公开(公告)号：JPH07272500A
公开(公告)日：1995-10-20
申请号：JP7186195
申请日：1995-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To improve and facilitate the measurement of the distribution of threshold voltage in a non-volatile memory-cell further. CONSTITUTION: A circuit device 1 for measuring the distribution of threshold voltage has a differential amplifier 3 connected to a circuit leg containing a memory-cell 2 and a reference circuit leg 4 and a circuit means unbalancing the values of currents flowing through each circuit leg. The circuit means comprises a variable current generator related to the reference circuit leg 4, the variable current generator is connected between a supply-voltage Vdd reference point and a ground-voltage GND reference point, and a current I2 as the function of supply voltage Vdd is generated in the reference circuit leg 4.
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公开(公告)号：JPH07264040A
公开(公告)日：1995-10-13
申请号：JP26549394
申请日：1994-10-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CORDINI PAOLO , PEDRAZZINI GIORGIO , ROSSI DOMENICO
IPC: H03K19/0175
Abstract: PURPOSE: To actualize an input/output stage which is arranged for operation with a low and a high voltage by mixed technologies. CONSTITUTION: The source-collector path of 1st and 2nd transistors(TR) M1 and M2 and the collector-source path of a 3rd TR M3 are connected across a power source in series, a diode D2 is connected in parallel to the source- collector path of the TR M2; and a circuit node A as the connection point between the cathode of the diode D2 and the collector of the TR M3 is regarded as an I/O terminal and connected to an input circuit 3, and the voltage from a drive circuit means is applied to the gate terminals of the TRs M1 to M3.
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公开(公告)号：JPH07262792A
公开(公告)日：1995-10-13
申请号：JP30221994
申请日：1994-12-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA
Abstract: PURPOSE: To reduce a chip area by unnecessitating any protection memory cell by forming a combined circuit for generating a signal for inhibiting the selection of any memory cell. CONSTITUTION: A non-volatile register 1 is formed from memory cells MC0-MCn and a redundant word line selection circuit 2. The cells MC0-MCn have output signals CMP0-CMPn to be activated when row address signals are coincident with memories. The selection circuit 2 inputs all the signals CM0-CMPn and generates signals RS0-RSi for selecting any one redundant line word and preventing the defective word line of which the address is coincident with the address stored in the register from being selected. Besides, a combined circuit 3 generates a signal DIS for inhibiting the selection circuit 2 from generating the signals RS0-RSi. The protection memory cell is unnecessitated by a redundant circuit formed from the selection circuit 2 and the combined circuit 3.
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公开(公告)号：JPH07254296A
公开(公告)日：1995-10-03
申请号：JP30490094
申请日：1994-12-08
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO
Abstract: PURPOSE: To provide an integrated circuit for checking the use rate of a redundant memory element inside a semiconductor memory device. CONSTITUTION: A redundant circuit is provided with a programmable nonvolatile memory register 1 for respectively storing the addresses of defective memory elements. When the stored address is coincident with supplied address signals A0-An, a redundant select signal RS is generated. Besides, the signals A0-A1 are supplied to combined circuit means 3 and 9 of the redundant circuit and when a suppress signal DIS' is supplied to the register 1 and the signals A0-An are coincident with the addresses stored in the non-programmed register 1, the generation of the redundant select signal RS is suppressed. When a control signal CHKN is activated, a multiplexer circuit means 11 under the control of the signal CHKN transmits the signal RS to and output pad 17 and when the generation of the signal DIS' is activated, the signal CHKN disturbs that generation.
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公开(公告)号：JPH07240858A
公开(公告)日：1995-09-12
申请号：JP23539494
申请日：1994-09-29
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： MANCUSO MASSIMO , POLUZZI RINALDO , RIZZOTTO GIANGUIDO
Abstract: PURPOSE: To provide a filter architecture optimizable and easily executable by using fuzzy logic. CONSTITUTION: This filter is provided with a filter circuit 2 for separating high band components and low band components from input signals for video images, a brilliance estimating circuit 6 for obtaining the mean brilliance value of respective plural sections for which the video images are divided, first and second video characteristic adjustment circuits 4 and 5 for changing the high band components and the low band components in response to the mean brilliance value and a totaling circuit 36 for combining the changed high band components and low band components and generating filtered video signals.
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