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    ＥＭＩ 쉴드된 반도체 패키지 및 ＥＭＩ 쉴드된 기판 모듈
    11.
    发明公开
    ＥＭＩ 쉴드된 반도체 패키지 및 ＥＭＩ 쉴드된 기판 모듈 无效
    EMI屏蔽半导体封装和EMI屏蔽基板模块

    公开(公告)号：KR1020130035620A

    公开(公告)日：2013-04-09

    申请号：KR1020110100033

    申请日：2011-09-30

    Applicant: 삼성전자주식회사

    Inventor： 김태훈 ,  김영룡 ,  김형섭 ,  김길수

    IPC: H01L23/60

    CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: PURPOSE: An EMI shielded semiconductor package and an EMI shielded substrate module are provided to improve productivity by performing a shielding process with a mounting substrate level. CONSTITUTION: An EMI shield layer(120) is formed in a part of a semiconductor package surface. The EMI shield layer includes a matrix layer(121), a metal layer(129), and a first seed particle(123). The metal layer is located on the upper side of the matrix layer. The first seed particle is located in an interface between the matrix layer and the metal layer and includes core particles(123a,125a) and surface reforming layers(123b,125b).

    Abstract translation: 目的：提供EMI屏蔽半导体封装和EMI屏蔽衬底模块，以通过执行具有安装衬底级别的屏蔽工艺来提高生产率。 构成：在半导体封装表面的一部分中形成EMI屏蔽层（120）。 EMI屏蔽层包括基质层（121），金属层（129）和第一种子颗粒（123）。 金属层位于基体层的上侧。 第一种子颗粒位于基质层和金属层之间的界面中，并且包括核心颗粒（123a，125a）和表面重整层（123b，125b）。

    웨이퍼 레벨 패키지 및 그 제조방법
    14.
    发明公开
    웨이퍼 레벨 패키지 및 그 제조방법 无效
    WAFER LEVEL PACKAGE AND METHOD FOR MANUFACTURING SAME

    公开(公告)号：KR1020080094251A

    公开(公告)日：2008-10-23

    申请号：KR1020070038423

    申请日：2007-04-19

    Applicant: 삼성전자주식회사

    Inventor： 장철용 ,  이종호 ,  윤철중 ,  김영룡 ,  안은철

    IPC: H01L23/12

    CPC classification number: H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/81 ,  H01L23/522 ,  H01L23/49816 ,  H01L24/10

    Abstract: A wafer level package is provided to simplify the whole process by a wafer level process by using a CoC(chip on chip) structure using a flip chip technique. A semiconductor chip(110) electrically comes in contact with a wafer(100). The semiconductor chip is coated with a first insulation layer(130). A first redistribution line is disposed on the first insulation layer, electrically connected to the wafer. A first external connection terminal(150) is attached to the first redistribution line. A second insulation layer(140) can be disposed on the wafer, exposing a part of the first external connection terminal. The wafer and the semiconductor chip can come in contact with each other in a manner that the active surface of the wafer confronts the active surface of the semiconductor chip.

    Abstract translation: 提供晶片级封装以通过使用倒装芯片技术通过使用CoC（片上芯片）结构通过晶片级处理简化整个过程。 半导体芯片（110）与晶片（100）电接触。 半导体芯片被涂覆有第一绝缘层（130）。 第一再分配线设置在第一绝缘层上，电连接到晶片。 第一外部连接端子（150）附接到第一再分配线。 第二绝缘层（140）可以设置在晶片上，暴露第一外部连接端子的一部分。 晶片和半导体芯片可以以使得晶片的有源表面面对半导体芯片的有源表面的方式相互接触。

    반도체 칩 패키지 및 이를 포함하는 반도체 패키지의 제조방법
    15.
    发明授权
    반도체 칩 패키지 및 이를 포함하는 반도체 패키지의 제조방법 失效
    制造半导体芯片封装的方法和包括其的半导体封装

    公开(公告)号：KR100836769B1

    公开(公告)日：2008-06-10

    申请号：KR1020070059597

    申请日：2007-06-18

    Applicant: 삼성전자주식회사

    Inventor： 이종호 ,  안은철 ,  윤철중 ,  오민호 ,  김영룡 ,  윤태성 ,  유철준

    IPC: H01L23/12

    CPC classification number: H01L2224/13 ,  H01L2224/73104

    Abstract: A semiconductor chip package and a manufacturing method thereof are provided to improve solder bonding reliability by forming a molding layer, which covers an active surface of a semiconductor chip and has a meniscus concave surface. A semiconductor chip(110) includes an active surface having bonding pads thereon, a rear surface, and a side surface. The rear surface is opposed to the active surface. Solder balls(112) for bumps are provided on the bonding pads of the semiconductor chip. The solder balls electrically couple the semiconductor chip with an external circuit. A molding layer(120c) covers the active surface of the semiconductor chip and exposes a portion of the solder balls. The molding layer has a meniscus concave surface, which includes an edge adjoined with the solder balls between the adjacent solder balls. The solder balls have a cross-section, which is parallel to the active surface and has a maximum diameter.

    Abstract translation: 提供半导体芯片封装及其制造方法，以通过形成覆盖半导体芯片的有源表面并具有弯月面凹面的成型层来提高焊接接合可靠性。 半导体芯片（110）包括其上具有接合焊盘的活性表面，后表面和侧表面。 后表面与活性表面相对。 用于凸块的焊球（112）设置在半导体芯片的接合焊盘上。 焊球将半导体芯片与外部电路电耦合。 模制层（120c）覆盖半导体芯片的有源表面并暴露一部分焊球。 成型层具有弯月面凹面，其包括与相邻焊球之间的焊球相邻的边缘。 焊球具有平行于活性表面并具有最大直径的横截面。

    반도체 패키지
    19.
    发明公开
    반도체 패키지 无效
    半导体封装

    公开(公告)号：KR1020140049199A

    公开(公告)日：2014-04-25

    申请号：KR1020120115036

    申请日：2012-10-16

    Applicant: 삼성전자주식회사

    Inventor： 장재권 ,  김영룡 ,  박진우 ,  장애니

    IPC: H01L23/12 ,  H01L23/48

    CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/81193 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/15311

    Abstract: A semiconductor package is provided. The semiconductor package according to an embodiment of the present invention, includes a lower semiconductor chip; and an upper semiconductor chip which is flip-chip-bonded to the lower semiconductor chip. The lower and the upper semiconductor chip include a first bonding pad which is formed on an active surface where a center line extended in a first direction is defined, and a first redistribution line which includes a first and a second connection region which are electrically connected to the first bonding pad and are arranged in an opposite direction with the same distance from the center line in a second direction vertical to the first direction.

    Abstract translation: 提供半导体封装。 根据本发明的实施例的半导体封装包括下半导体芯片; 以及将下半导体芯片倒装芯片接合的上半导体芯片。 下半导体芯片和上半导体芯片包括形成在沿着第一方向延伸的中心线的有源表面上的第一焊盘，以及包括第一和第二连接区域的第一再分配线，该第一和第二连接区域电连接到 所述第一焊盘并且在与所述第一方向垂直的第二方向上以与所述中心线相同的距离的相反方向布置。

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