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公开(公告)号：KR1020120116335A
公开(公告)日：2012-10-22
申请号：KR1020120026571
申请日：2012-03-15
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A radar device is provided to improve the reliability of measurement by using a digital modulation-demodulation technology. CONSTITUTION: A transmitting unit(110) converts a digital modulation signal generated by a digital signal processing unit(130) into a carrier frequency through analog conversion. The transmitting unit transmits a generated transmission signal(T1) through a transmission antenna(141). A receiving unit(120) receives an echo signal(R1) reflected from a target(150) and performs digital conversion to the same. The digital signal processing unit demodulates the each signal. [Reference numerals] (130) Digital signal processing unit; (AA) Digital code
Abstract translation: 目的：提供雷达装置，通过数字调制解调技术提高测量的可靠性。 构成：发送单元（110）通过模拟转换将由数字信号处理单元（130）产生的数字调制信号转换为载波频率。 发送单元通过发送天线（141）发送生成的发送信号（T1）。 接收单元（120）接收从目标（150）反射的回波信号（R1），并对其进行数字转换。 数字信号处理单元解调每个信号。 （附图标记）（130）数字信号处理单元; （AA）数字代码
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公开(公告)号：KR1020120072219A
公开(公告)日：2012-07-03
申请号：KR1020100134054
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H04B1/16
CPC classification number: H04B1/30 , H03D3/008 , H04L25/063
Abstract: PURPOSE: A digital radio frequency reception apparatus is provided to reduce consumption power, area, and development costs by eliminating interference signals in a reception signal outputted from a rational decimator. CONSTITUTION: A mixer(140) eliminates IF(Intermediate Frequency) signals from output signals of a digital signal converter(130). An integer decimator(150) executes the integer decimeter of the phase-separated signal. A DC(Direct Current) offset compensator(160) eliminates DC(Direct Current) component from the processed signals. An IQ mismatch compensator(170) compensates phase errors of quadrature signal and in phase signal for the signal. A rational decimator(180) executes the rational decimation of the phase compensated signal. A channel selecting filter(190) eliminates interference signal from the signal.
Abstract translation: 目的：提供一种数字射频接收装置，通过消除从理性抽取器输出的接收信号中的干扰信号来降低功耗，面积和开发成本。 构成：混合器（140）消除来自数字信号转换器（130）的输出信号的IF（中频）信号。 整数抽取器（150）执行相分离信号的整数分米。 DC（直流）偏移补偿器（160）从处理的信号中消除DC（直流）分量。 IQ失配补偿器（170）补偿信号的正交信号和相位信号的相位误差。 理性抽取器（180）执行相位补偿信号的有理抽取。 信道选择滤波器（190）消除来自该信号的干扰信号。
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公开(公告)号：KR101029611B1
公开(公告)日：2011-04-15
申请号：KR1020080132492
申请日：2008-12-23
Applicant: 한국전자통신연구원
Abstract: 본 발명의 일 실시예에 따른 이동 평균 필터는, 이산 시간(Discrete-time) RF 기술에서 RF 신호의 이산 시간 신호처리를 위해 아날로그 필터 대신에 통상적으로 사용되는 저주파대역 통과 특성을 갖는 종래의 이동 평균 필터과는 달리, 고주파대역 통과 특성을 갖는다. 본 발명에 의한 고주파대역 통과필터를 이용함으로써 기존의 아날로그 신호처리 영역에서 특정한 트랜시버 구조를 위해 소요되던 고주파대역 통과필터를 능동소자에 의존하지 않고 고도로 정밀한 특성제어가 가능한 수동소자와 스위치의 조합으로 구성되는 디지털 회로로 구현이 가능하다.
이동 평균 필터, Moving Average Filter, FIR, Discret-time RF-
公开(公告)号：KR1020100064309A
公开(公告)日：2010-06-14
申请号：KR1020090055583
申请日：2009-06-22
Applicant: 한국전자통신연구원
CPC classification number: H03L7/0991 , H03L7/093
Abstract: PURPOSE: A linear apparatus of a digital controlled oscillator applies is provided to apply the digital controlled oscillator to a direct modulation method of a mobile communication transmitter by gaining a linear property. CONSTITUTION: A first filter outputs only a signal of a low frequency band of an input signal to a digital controlled oscillator. A negative feedback loop successively passes through the signal of an input end, a frequency table and a frequency band digital code mapper. The negative feedback loop revises the input of the digital controlled oscillator by making negative feedback the signal to the input end of the first filter. A frequency table generator stores a frequency value of an output signal of the digital controlled oscillator on the frequency table. The negative feedback loop includes the frequency table(220) and frequency band digital code mapper(210).
Abstract translation: 目的：提供数字控制振荡器的线性装置，以通过获得线性特性将数字控制振荡器应用于移动通信发射机的直接调制方法。 构成：第一个滤波器只将输入信号的低频带信号输出到数字控制振荡器。 负反馈环路依次通过输入端的信号，频率表和频带数字码映射器。 负反馈环路通过将信号反馈到第一滤波器的输入端来修正数字控制振荡器的输入。 频率表发生器将数字控制振荡器的输出信号的频率值存储在频率表上。 负反馈回路包括频率表（220）和频带数字码映射器（210）。
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公开(公告)号：KR1020100063638A
公开(公告)日：2010-06-11
申请号：KR1020090063462
申请日：2009-07-13
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A digital intensive RF receiver is provided to perform per-narrow band noise shaping of desired band, thereby it is being favorable for digital design by removing necessity of a RF tuner, when IF(Intermediate Frequency) signal or frequency band signal centered by DC(Direct Current) is transformed through sub-sampling A/D transform. CONSTITUTION: A sub-sampling A/D(Analog to Digital) converter(400) transforms RF(Radio Frequency) signal of the second filter unit to digital signal according to sub-sampling clock of clock generation unit(300). In a A/D conversion process, the sub-sampling A/D converter divides the RF signal to a plurality of frequency bands. The sub-sampling A/D converter performs a plurality of noise shaping by sub channels in the RF signal. According to a system clock, a digital processing unit(500) processes the digital signal.
Abstract translation: 目的：提供数字密集型射频接收机，以执行所需频带的每个窄带噪声整形，从而通过消除RF调谐器的必要性有利于数字设计，当IF（中频）信号或频带信号以 DC（直流）通过子采样A / D变换进行变换。 构成：子采样A / D（模拟到数字）转换器（400）根据时钟产生单元（300）的子采样时钟将第二滤波器单元的RF（射频）信号转换为数字信号。 在A / D转换处理中，副采样A / D转换器将RF信号分成多个频带。 子采样A / D转换器通过RF信号中的子信道执行多个噪声整形。 根据系统时钟，数字处理单元（500）处理数字信号。
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Patent Agency Ranking
公开(公告)号：KR1020100063636A
公开(公告)日：2010-06-11
申请号：KR1020090055584
申请日：2009-06-22
Applicant: 한국전자통신연구원
CPC classification number: H01L28/40 , H03B5/1228 , H03B5/1243 , H03B2201/0208 , H03L7/099
Abstract: PURPOSE: A capacitor with variable capacitance and a digital control oscillator thereof are provided to reduce power consumption or the area of a chip by reducing the use of a digital circuit block which is used for improving the frequency resolution of a digital phase locked loop frequency synthesizer. CONSTITUTION: A lamination structure(10) comprises a plurality of metal layers including a first metal layer(111) and a plurality of dielectric layers(121,122) which are inserted between a plurality of metal layers. A switching unit, which has at least one switch, is connected to at least one metal layer among the metal layers excluding the first metal layer. The first metal layer and one end of the switch are used as a positive terminal of the capacitor. Two or more capacitances are provided through the short-circuit and open control of the switch.
Abstract translation: 目的：提供具有可变电容的电容器及其数字控制振荡器，以通过减少用于提高数字锁相环频率合成器的频率分辨率的数字电路块的使用来降低功耗或芯片面积 。 构成：层叠结构（10）包括多个金属层，包括插入在多个金属层之间的第一金属层（111）和多个电介质层（121,122）。 具有至少一个开关的切换单元连接到除了第一金属层之外的金属层中的至少一个金属层。 第一金属层和开关的一端用作电容器的正极。 通过开关的短路和开路控制提供两个或多个电容。
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公开(公告)号：KR1020100062880A
公开(公告)日：2010-06-10
申请号：KR1020090050961
申请日：2009-06-09
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A digital DC offset correcting method and an apparatus are provided to regularly maintain an output DC offset value of a filter and discrete-time amplifier by changing an input code value of a digital-analog converter. CONSTITUTION: A digital-analog converter(310) generates an initial voltage value of the load capacitor by charging a load capacitor according to an input code value. A comparator(320) connects a discrete-time amplifier and a filter(340) with the load capacitor. The comparator compares the discrete-time amplifier and the output of the filter with the predetermined output DC offset value according to the initial voltage value. A controller(330) changes the input code value of the digital-analog converter according to a result of the comparator.
Abstract translation: 目的：提供数字DC偏移校正方法和装置，通过改变数模转换器的输入码值来定期地保持滤波器和离散时间放大器的输出DC偏移值。 构成：数模转换器（310）通过根据输入代码值对负载电容器充电来产生负载电容器的初始电压值。 比较器（320）将离散时间放大器和滤波器（340）连接到负载电容器。 比较器根据初始电压值将离散时间放大器和滤波器的输出与预定的输出DC偏移值进行比较。 控制器（330）根据比较器的结果改变数模转换器的输入代码值。
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公开(公告)号：KR1020100062806A
公开(公告)日：2010-06-10
申请号：KR1020090023897
申请日：2009-03-20
Applicant: 한국전자통신연구원
CPC classification number: H03L7/1075 , H03L7/085 , H03L7/093 , H03L7/1976
Abstract: PURPOSE: A frequency adjustment loop is provided to form a lock state of the frequency adjustment loop within fast time by moving an output frequency of an oscillator to wanting frequency band. CONSTITUTION: An oscillator(140) controls an output frequency according to inputted control bit. A programmable divider(150) divides the output frequency of the oscillator according to varied dividing ratio. A counter unit(110) is inputted an output signal of the programmable divider and a reference frequency. The counter unit measures a clock number of the output signal of the divider in one period of the reference frequency. A frequency detector(120) outputs the value tacking out from the clock number outputted from the counter unit in a standard comparison value to a control bit of the oscillator. The programmable divider decides the divide ratio about the output signal of the oscillator by receiving a feedback the clock number outputted from the counter unit.
Abstract translation: 目的：通过将振荡器的输出频率移动到想要的频带，提供频率调整回路以在快速时间内形成频率调节回路的锁定状态。 构成：振荡器（140）根据输入的控制位控制输出频率。 可编程分频器（150）根据分频比分频振荡器的输出频率。 计数器单元（110）输入可编程分频器的输出信号和参考频率。 计数器单元在参考频率的一个周期内测量分频器的输出信号的时钟数。 频率检测器（120）将从标准比较值中的从计数器单元输出的时钟编号输出的值输出到振荡器的控制位。 可编程分频器通过从计数器单元输出的时钟数字接收反馈来决定关于振荡器输出信号的分频比。
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公开(公告)号：KR100942697B1
公开(公告)日：2010-02-16
申请号：KR1020070121639
申请日：2007-11-27
Applicant: 한국전자통신연구원
IPC: H03B5/12
CPC classification number: H03B5/1231 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1253
Abstract: 본 발명은 커패시티브-디제너레이션 이중교차결합 전압제어발진기에 관한 것으로, 공진부의 제1 및 제2 출력노드에 교차 결합된 발진 트랜지스터쌍을 구비하여 발진 동작을 수행하는 주교차 결합 발진부; 및 상기 공진부의 제1 및 제2 출력노드와 상기 주교차 결합 발진부의 트랜지스터쌍에 대해 교차 결합된 정궤환 트랜지스터쌍과 상기 정궤환 트랜지스터쌍의 에미터간에 연결된 디제너레이션 커패시턴스를 구비하여, 상기 주교차 결합 발진부의 부성 저항을 증대시키는 보조교차 결합 발진부를 포함하여 구성되며, 이에 의하여 최대획득가능 발진 주파수를 증대하면서 입력 커패시턴스는 감소될 수 있도록 한다.
전압제어발진기, 커패시티브-디제너레이션, 이중교차결합, 부성 저항-
公开(公告)号：KR1020090109969A
公开(公告)日：2009-10-21
申请号：KR1020080035488
申请日：2008-04-17
Applicant: 한국전자통신연구원
CPC classification number: H01L23/10 , B81B7/007 , B81C2203/0118 , H01L24/45 , H01L24/48 , H01L24/94 , H01L2224/16145 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1461 , H01L2924/16235 , H01L2924/00 , H01L2924/2076 , H01L2224/05599
Abstract: PURPOSE: A wafer level package and method for manufacturing the same are provided to form the telecommunication line of the package internal unit without the separate via process of passing through a substrate. CONSTITUTION: The wafer level package includes the first substrate(220), the input-output pad(222), the second substrate(210), and the solder. The first substrate includes the common duct in which the first internal units are positioned. The input-output pad is formed in the first top of the substrates. The input-output pad is electrically connected to the first internal units. The second substrate is positioned on the first substrate. The second substrate corresponds to the input-output pad is removed. The solder joins the first substrate and the second substrate.
Abstract translation: 目的：提供晶片级封装及其制造方法，以形成封装内部单元的电信线路，而不需要通过基板的单独的通孔工艺。 构成：晶片级封装包括第一衬底（220），输入 - 输出焊盘（222），第二衬底（210）和焊料。 第一基板包括第一内部单元所在的公共管道。 输入 - 输出焊盘形成在基板的第一顶部。 输入 - 输出焊盘电连接到第一内部单元。 第二基板位于第一基板上。 第二个衬底对应于输入 - 输出垫被去除。 焊料与第一基板和第二基板接合。
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